Transcript CHAP3-1 - Department of Computer Engineering

VLSI Design
Lecture 5: Logic Gates
Mohammad Arjomand
CE Department
Sharif Univ. of Tech.
Adapted with modifications from Wayne Wolf’s lecture notes
Topics
Combinational logic functions.
 Static complementary logic gate structures.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Combinational logic expressions
Combinational logic: function value is a
combination of function arguments.
 A logic gate implements a particular logic
function.
 Both specification (logic equations) and
implementation (logic gate networks) are
written in Boolean logic.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Gate design
Why designing gates for logic functions is
non-trivial:
– may not have logic gates in the libray for all
logic expressions;
– a logic expression may map into gates that
consume a lot of area, delay, or power.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Boolean algebra terminology

Function:
f = a’b + ab’
a is a variable; a and a’ are literals.
 ab’ is a term.
 A function is irredundant if no literal can be
removed without changing its truth value.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Completeness
A set of functions f1, f2, ... is complete iff
every Boolean function can be generated by
a combination of the functions.
 NAND is a complete set; NOR is a
complete set; {AND, OR} is not complete.
 Transmission gates are not complete.
 If your set of logic gates is not complete,
you can’t design arbitrary logic.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Static complementary gates
Complementary: have complementary
pullup (p-type) and pulldown (n-type)
networks.
 Static: do not rely on stored charge.
 Simple, effective, reliable; hence
ubiquitous.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Static complementary gate
structure
Pullup and pulldown networks:
VDD
pullup
network
out
inputs
pulldown
network
VSS
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Inverter
+
a
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out
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Inverter layout
VDD
+
a
tub ties
out transistors
a
out
(tubs not
shown)
GND
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NAND gate
+
out
b
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a
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NAND layout
VDD
+
out
b
a
out tub
ties
b
a
GND
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NOR gate
+
b
a
out
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NOR layout
b
VDD
a
tub ties
b
out
out
a
GND
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
AOI/OAI gates
AOI = and/or/invert; OAI = or/and/invert.
 Implement larger functions.
 Pullup and pulldown networks are compact:
smaller area, higher speed than
NAND/NOR network equivalents.
 AOI312: and 3 inputs, and 1 input
(dummy), and 2 inputs; or together these
terms; then invert.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
AOI example
out = [ab+c]’:
invert
symbol
circuit
or
and
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Copyright  2008 Wayne Wolf
Pullup/pulldown network design
Pullup and pulldown networks are duals.
 To design one gate, first design one
network, then compute dual to get other
network.
 Example: design network which pulls down
when output should be 0, then find dual to
get pullup network.

Modern VLSI Design 4e: Chapter 3
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Dual network construction
a
c
b
b
dummy
a
c
dummy
Modern VLSI Design 4e: Chapter 3
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Logic levels
Solid logic 0/1 defined by VSS/VDD.
 Inner bounds of logic values VL/VH are not
directly determined by circuit properties, as
in some other logic families.

VDD
logic 1
unknown
VSS
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VH
VL
logic 0
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Logic level matching

Levels at output of one gate must be
sufficient to drive next gate.
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Transfer characteristics

Transfer curve shows static input/output
relationship—hold input voltage, measure
output voltage.
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Inverter transfer curve
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Logic thresholds
Choose threshold voltages at points where
slope of transfer curve = -1.
 Inverter has a high gain between VIL and
VIH points, low gain at outer regions of
transfer curve.
 Note that logic 0 and 1 regions are not equal
sized—in this case, high pullup resistance
leads to smaller logic 1 range.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Noise margin
Noise margin = voltage difference between
output of one gate and input of next. Noise
must exceed noise margin to make second
gate produce wrong output.
 In static gates, t= voltages are VDD and
VSS, so noise margins are VDD-VIH and VILVSS.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
CMOS Inverter:
Transfer characteristic (Review)
A: N: off P: linear
C: N: saturated P: saturated
E: N: linear P: off
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B: N: saturated P: linear
D: N: linear P: saturated
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Device Models (Review)
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2
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6
Delay

Assume ideal input (step), RC load.
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Delay assumptions

Assume that only one transistor is on at a
time. This gives two cases:
– rise time, pullup on;
– fall time, pullup off.

Assume resistor model for transistor.
Ignores saturation region and
mischaracterizes linear region, but results
are acceptable.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Current through transistor

Transistor starts in saturation region, then
moves to linear region.
Modern VLSI Design 4e: Chapter 3
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Capacitive load



Most capacitance
comes from the next
gate.
Load is measured or
analyzed by Spice.
Cl: load presented by
one minimum-size
transistor.
Modern VLSI Design 4e: Chapter 3
CL = S (W/L)i Cl
Copyright  2008 Wayne Wolf
Resistive model for transistor

Average V/I at two voltages:
– maximum output voltage
– middle of linear region

Voltage is Vds, current is given Id at that
drain voltage. Step input means that Vgs =
VDD always.
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Resistive approximation
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Ways of measuring gate delay
Delay: time required for gate’s output to
reach 50% of final value.
 Transition time: time required for gate’s
output to reach 10% (logic 0) or 90% (logic
1) of final value.

Modern VLSI Design 4e: Chapter 3
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Inverter delay circuit

Load is resistor + capacitor, driver is
resistor.
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Inverter delay with t model
t model: gate delay based on RC time
constant t.
 Vout(t) = VDD exp{-t/(Rn+RL)/ CL}
 tf = 2.2 R CL
 For pullup time, use pullup resistance.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
t model inverter delay

0.5 micron process:
– Rn = 6.47 kW
– Cl = 0.89 fF
– CL = 1.78 fF

So
– td = 0.69 x 6.47E3 x 1.78E-15 = 7.8 ps.
– tf = 2.2 x 6.47E3 x 1.78E-15 = 26.4 ps.
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Copyright  2008 Wayne Wolf
Quality of RC approximation
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Power consumption analysis
Almost all power consumption comes from
switching behavior.
 Static power dissipation comes from
leakage currents.
 Surprising result: power consumption is
independent of the sizes of the pullups and
pulldowns.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Other models

Current source model (used in power/delay
studies):
– tf = CL (VDD-VSS)/Id
– = CL (VDD-VSS)/0.5 k’ (W/L) (VDD-VSS -Vt)2

Fitted model: fit curve to measured circuit
characteristics.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Power consumption circuit

Input is square wave.
Modern VLSI Design 4e: Chapter 3
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Power consumption
A single cycle requires one charge and one
discharge of capacitor: E = CL(VDD - VSS)2 .
 Clock frequency f = 1/t.
 Energy E = CL(VDD - VSS)2.
 Power = E x f = f CL(VDD - VSS)2.

Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Observations on power
consumption
Resistance of pullup/pulldown drops out of
energy calculation.
 Power consumption depends on operating
frequency.

– Slower-running circuits use less power (but not
less energy to perform the same computation).
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf
Speed-power product
Also known as power-delay product.
 Helps measure quality of a logic family.
 For static CMOS:

– SP = P/f = CV2.

Static CMOS speed-power product is
independent of operating frequency.
– Voltage scaling depends on this fact.
Modern VLSI Design 4e: Chapter 3
Copyright  2008 Wayne Wolf