Transcript DEPFET pixel detectors

Design and Technology of DEPFET
Active Pixel Sensors for Future e+eLinear Collider Experiments
G. Lutza, L. Andriceka, P. Fischerb, K. Heinzingerc, P. Lechnerc,
I.Pericd, M. Reichee, R.H. Richtera, G. Schallera, M. Schneckea, F.
Schoppera, H. Soltauc, L. Strüdera, J. Treisa, M. Trimpld, J. Ulricid,
N. Wermesd
a)MPI Halbleiterlabor Munich, Germany
b)University of Mannheim, Germany
c)PNSensor gGmbH Munich, Germany
d)University of Bonn, Germany
e)MPI für Mikrostrukturphysik Halle, Germany
Content
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Introduction
DEPFET principle and properties
DEPFET pixel detectors
Pixel detector prototypes (for LC and X-ray astronomy)
Module concept
Steering and readout chip
Matrix Test results
Power consumption
Conclusion
Introduction
• Requirements for Linear colliders (example: TESLA)
– Precise vertexing with low momentum tracks requires:
• High granularity pixel detectors
• Low multiple scattering  thin detectors, avoidance of
cooling of sensor  low power consumption
• Limitation of occupancy  sufficiently high readout
speed
• DEPFET pixel detectors are able to fulfill these requirements
– Due to particular function principle
– Developed and built in own laboratory of the MPI
– Electronics and system developed in close collaboration
with Universities Bonn and Mannheim
DEPFET principle and properties
DEPFET structure
and device symbol
Function principle
– Field effect transistor on top of fully depleted bulk
– All charge generated in fully depleted bulk; assembles
underneath the transistor channel; steers the transistor
current
– Clearing by positive pulse on clear electrode
– Combined function of sensor and amplifier
DEPFET principle and properties
DEPFET structure
and device symbol
Properties
– low capacitance ► low noise
– Signal charge remains undisturbed by readout ► repeated readout
– Complete clearing of signal charge ► no reset noise
– Full sensitivity over whole bulk ► large signal for m.i.p.; X-ray sens.
– Thin radiation entrance window on backside ► X-ray sensitivity
– Charge collection also in turned off mode ► low power consumption
– Measurement at place of generation ► no charge transfer (loss) ►
Operation over very large temperature range ► no cooling needed
DEPFET Operation: Energy Resolution
Circular DEPFET out of
Prototype DEPFET pixel
fabrication run at MPI
Setup:
source follower read out
commercial pre-amp
shaping time 6 μs
Result at Room Temperature:
 131 eV @ 5.9 keV
 2.2 el. r.m.s.
DEPFET Pixel Detector Operation Mode
Large area covered
with DEPFETS
Individual transistors
or rows of transistors
Can be selected for
readout
All other transistors
are turned off
Those are still able
to collect signal
charge
Very low power
consumption
DEPFET pixel detector prototypes
Two projects on same wafer, two different geometries:
XEUS (future X-ray observatory):
Circular (enclosed) geometry
Source readout
Linear collider:
Rectangular geometry
Drain readout
DEPFET Technology at HLL extended:
Double poly / double metal process
Summary of technology properties
1. Test diodes (fully depleted 450 μm)
cut perpendicular to channel (with clear)
 Vdep = 30..40 V and 130..150 V
 Ileak = 100..200 pA/cm2
metal I
 Vfb = -1 V
gate
poly II
2. ILD Quality (Breakdown Voltage)
 Poly I to Si:
VB > 100 V
 Poly II to Si:
VB > 100 V
 Metal I to Si:
VB > 200 V
 Poly I to Poly II:VB > 20 V
n+ clear
deep p implant
p channel implant
clear gate
poly I
n internal gate
Pixel prototype production (6“ wafer)
for XEUS and LC (TESLA)
Aim: Select design options for an optimized array operation
(no charge loss, high gain, low noise, good clear operation)
On base of these results => production of full size sensors
Many test arrays
- Circular and linear DEPFETS
up to 128 x 128 pixels
minimum pixel size about 30 x 30 µm²
- variety of special test structures
•Structures requiring only one
metalization layer
•Production up to first metal layer finished
•Test results agree very well with
•device simulations
The LC sensor matrix


rectangular double pixels (common
source)
Depletion type p-channel MOSFETs
linear transistors (small pixels)
drain

double pixel cell 33 x 47 µm2
in DEPFET-Matrix
gate
reset
16x128 DEPFET-Matrix
DEPFET measurements
on rectangular test transistors
(W = 120µm L = 5µm)
Output characteristics:
Correct transistor behavior
Transfer characteristics:
Device can be completely
switched off
Transistor parameters
agree with simulation
Module concept
Thin (50µm) DEPFET pixel detector
supported by silicon stiffening frame
Row selection electronics on long side of frame
(Analog) readout electronics at short end
Thin detector technology already developed
tested with diodes so far
to be describe by
L. Andricek on Wednesday
DEPFET Matrix Read Out: ASICs
Development at the Universities Bonn and Mannheim
CURO II:
4.6 mm
4.5 mm
Switcher II:
4.8 mm
Readout row selection chip
• AMS 0.8µm HV
• high speed
• high voltage range (20V)
• 64 rows=2x64 channels
• daisy chainable
4.5 mm
Fast RO chip for DEPFETs
• TSMC 0.25µm, 5 metal
• 128 channels „CUrrent ReadOut“
• fast current based memory cells
• hit identification + zero suppression
• Correlated double sampling within 40ns
Status readout electronics
• Not yet designed for low power consumption in
waiting period between pulse trains
• Not yet optimally matched to desired pixel geometry
Row selection chip
CURO readout chip
RAM & sequencer tested
up to 80 MHz
Analog performance ok to 30 MHz
Drives signals in range 0 to 20V
Digital part, the hit-finder and the
current-comparator-block both work
with desired speed of 50MHz
Analog part (memory cell):
speed: 25MHz
accuracy: 0.1 %
noise : < 30 electrons
Power consumption at 50MHz:
~ 400mW / chip with active channel
~ 10mW / chip for others
Power consumption 2 mW/channel
Readout of complete DEPFETmatrix
So far only available for XEUS project
• Different conditions:
• Source readout
• 8-fold double correlated
sampling
• Slow readout: 13µs/row
FWHM of Mn-Ka (5.9keV): 155.1 eV
ENC: 11.5 e-
55Fe
source spectrum in logarithmic scale
Vertex Detector for Linear Collider
sensitive area 1st layer module: 100x13 mm2, 2nd-5th layer : 125x22 mm2 
∑120 modules
TESLA TDR:
• close
to IP, r = 15 mm (1st layer)
• pixel size: 20-30 μm
• ~0.1% X0 per layer
• overall: ~ 1GPixel
• 5 barrels – stand alone tracking
TESLA TDR Design
Module Power consumption during pulse train
Readout channels=2xnb.of columns
Layer 1:
2x512=1024
Layer 2-5:
2x820=1640
Switcher channels=nb.of double rows
Layer 1 :
4000/2=2000
Layer 2-5 :
5000/2=2500
• Thin Detector region (layer 2-5)
– Sensor: two active rows
1640x5Vx100µA= 820mW
– Switcher: 1 active channel
300mW
4999 passive channels
2500x0.15mW= 375mW
– Total in thin detector region during pulse train
1.5W
• End hybrid region
– CURO R/O chip :
820x2 channels x 2mW=
3.3W
Vertex detector power consumption
• During beam train
– In thin detector region 120x 1.5W=180W
– In cooled end region 120x 3.3W=400W
• With electronics power turned off in between trains (TESLA)
reduction by factor ~ 1/200
– In thin detector region 180W/200 = 0.9W
– In cooled end region 400W/200 = 2.0W
Conclusions
• DEPFET Pixel detectors use radically different
function principle from other pixel detectors
• Properties are very well suited for LC applications
• High S/N ratio at large speed and low power
consumption can be obtained for thin detectors
• Detector fabrication is done in own laboratory
• Development program is well advanced
Performance of Prototype R/O Chip
digital part: the hit-finder and the current-comparator-block
both work with desired speed (50MHz)
analog part (memory cell):
speed: 25MHz
accuracy: 0.1 %
noise : < 30 electrons
350
2,0
Samplenoise of memory cell
Accuracy of memory cell
1,8
300
1,4
250
-
200
m = 27,74 +/- 0,44 e / sample
c = 15,82 +/- 3,6 e
150
Iout - Iin [µA]
noise [electrons]
1,6
1,2
0.1% accuracy reached
1,0
0,8
0,6
10nA
100
@ room-temperature
25 MHz - Samplefrequency
50
0,4
0,2
2
4
6
sqrt (samples)
8
10
12
0
10
20
30
40
Iinput [µA]
50
60
70
New Readout concept: CURO
CURO : CUrrent Read Out
 front end:
automatic pedestal subtraction
(double correlated sampling)
 analog currents buffered in FIFO
 Hit-Logic performs 0 suppression
and multiplexes hits to ADC
(ADC only digitizes hits !)
128 channels – CURO II
CURO II:
Features:
 TSMC 0.25µm, 5metal
4.5 mm
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


Full blown RO Chip with 128 channels
fast correlated double sampling
produced 11/2003
costs: 30k$
Currently under test
4.5 mm
new steering chip
Switcher II:
• AMS 0.8µm HV
• versatile sequencing chip
(internal sequencer  flexible pattern)
• high speed + high voltage range (20V)
• drives 64 DEPFET-rows
(can be daisy chained)
4.8 mm
4.6 mm
[I.Peric (Bonn) / P.Fischer (Mannheim)]
1
0
1
1
20ns
U = 20V
 = 30 MHz
Current based Readout
How to store a current ??
IBias
I In
input
output
ISTORE
sample
Storage phase: input and sample-switch closed :
 gate-capacitance of nmos charged
Sampling phase: input and sample-switch opened :
 voltage at capacitance „unchanged“
 current unchanged
I = I In + IBias
CGate
Transfer phase: output switch closed :
(done immediately after sampling)
 ISTORE is flowing out
CURO - Architecture
CURO : CUrrent Read Out
 front end:
automatic pedestal subtraction
(double correlated sampling)
- easy with currents  analog currents buffered in FIFO
 Hit-Logic performs 0 suppression
and multiplexes hits to ADC
(ADC only digitizes hits !)
TESLA Vertex Detector: Material Budget
Estimated Material Budget (1st layer):
Pixel area:
100x13 mm2, 50 μm : 0.05% X0
steer. chips:
100x2 mm2, 50 μm : 0.008% X0
(massive) Frame :100x4 mm2, 300 μm : 0.09% X0
reduce frame material!!!
 "support grid"
perforated frame: 0.05 % X0
total: 0.11 % X0
DEPFET Operation: Amplification
2D dynamic simulation of a MOSFET
hit response to a generation of 1600 e-h pairs
mip
prod. 2003: ~0.4 nA/e-
+


-+
+
+
generated electrons are collected in "internal gate" and modulate the transistor current
Signal charge removed via clear contact
DEPFET Operation: Charge Removal
measurement cycle: sample-clear-sample
complete "Clear"  no reset noise!
---
Source current (μA)
achieved with Vclear >11 V
(confirmed by noise measurements)
complete "Clear"
clear voltage (V)


generated electrons are collected in „internal gate“ and modulate the transistor current
Signal charge removed via "Clear" contact
Background at TESLA
Simulation:
High magnetic field to
„reduce“ background
But still:
Rate high ( 80 hits / mm bunchtrain )
One frame per Train:
Occupancy 20% !!!!!
[C.Büssser, DESY]