Transcript The CAST Experiment Search for Solar Axions

DEPFET development at the
MPI Semiconductor Laboratory
Gerhard Lutz
MPI-Semiconductor Laboratory, München
Vertex2003
Lake Windermere, Sept.16, 2003
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Content
Introduction
DEPFET detector-amplifier structure
 Principle and properties
 Applications
DEFETs as pixel detector
 In x-ray astronomy (XEUS)
 In particle colliders (TESLA)
DEPFET production in Munich
Vertex detector for TESLA
 Detector thinning technology
 Readout electronics
Summary and conclusions
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Introduction
 DEPFET detector development at Munich is
part of our activities in connection with instute experiments
 Own laboratory is supported by two Max-Planck Institutes
 Active in particle physics and astrophysics (X-ray astronomy)
 Complete semiconductor processing line in house
 Detectors mostly based on own concepts
 Present major project: DEPFET pixel detectors
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The Depleted Field Effect Transistor (DEPFET)
Kemmer+Lutz 1985
Device concept:
 Combination of FET
transistor with
 Sideward depletion
(Drift chamber)
Gatti + Rehak 1984
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DEPFET properties
DEPFET structure
and device symbol
 Field effect transistor on top of fully depleted bulk
 All charge generated in fully depleted bulk
assembles underneath the transistor channel
steers the transistor current
 Combined function of sensor and amplifier
 low capacitance and low noise
 Signal charge remains undisturbed by readout ► repeated readout
 Complete clearing of signal charge ► no reset noise
 Full sensitivity over whole bulk
 Thin radiation entrance window on backside
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Operation modes of DEPFET
DEPFET operation properties
 Charge collected and stored in internal gate both
in transistor on mode and also
in transistor off mode
 Charge is not destroyed by measuring it
DEPFET operation modes:
1) Normally on (continuous operation, occasional reset)
►real time operation
2) Normally off (charge collection in powerless condition)
►integration mode operation
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Simulations operation modes
Real time mode:
•Signal collection with DEPFET on
•Real time signal processing (shaping)
•Clear internal gate from time to time
Applications:
Readout element of drift detectors
or CCDs
Drain current
Charge in internal gate
Drain current
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Simulations operation modes
Integration and Sample mode:
•Signal collection with turned off DEPFET
•Turn on DEPFET by gate
•First current measurement
•Clear internal gate
•Remeasure current and take difference
Applications:
Building block of pixel detectors
Readout element of drift detectors
Drain current
Charge in internal gate
Drain current
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DEPFET types:
MOS-depletion
MOS-enhancement
JFET
Open (rectangular) geometry
Closed (circular) geometry
DEFET applications
•Readout element of
 Drift detector
 CCD
•Element of pixel detector
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DEPFET 55Fe Spectrum
Single DEPFET
(JFET, closed geometry)
At room temperature
Cooled
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MPI experiments needing DEPFETs
X-ray astronomy:
 XEUS (next
generationEuropean X-ray
observatory)
successor of XMM-Newton
Particle physics:
 TESLA vertex detector
Both experiments need pixel detectors
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DEPFET pixel matrix
Low power consumption
Fast random access to
specific array regions
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- Read filled cells of a row
- Clear the internal gates
of the row
-Read empty cells
Difference of readings
(filled/empty) mesures
12charge
Prototype DEPFET-System
developed with Bonn University
Control-Chip:
Switcher
64x64 pixel
DEPFET-Matrix
JFET type
Closed geometry
(50x50µm2 pixel)
 64 x 64 matrix with 50 x 50 µm2 pixel
 designed for Biomedical Applications
 clock rate : 50 kHz
 achieved noise in matrix: ~50e
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low noise
Readout-Chip:
CARLOS
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results with prototype system
Single-pixel spectra:
Matrix-picture with 55Fe:
Autoradiography with 3H:
Ka
6000
5000
# Zähler
4000
3000
2000
Escape - Peak
Kb
1000
0
2
4
6
Energie [keV]
55Fe-spectra
~ 3.2 mm
@ 300K
ENC = 4.8 +/- 0.1 e-
spatial resolution: ~ 9µm
(with 50x50 µm2 pixel)
~ 10 mm
detection of Tritium 3H
(5,6keV mean energy)
[J.Ulrici, Bonn]
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MPI semiconductor laboratory
800 m² cleanroom up to class 1 ...
mounting & bonding
... with modern, custom made facilities ...
test & qualification
... for a full 6‘‘ silicon process line
simulation, layout & data analysis
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Future X-ray Mission: XEUS
(X-ray Evolving Universe Spectroscopy)
Scientific aim:
investigation of the universe at an
early evolution stage:
- early black holes
- evolution and clustering of galaxies
- evolution of element synthesis
Experiment




Increase in collecting area (factor
100)
Increase of collection area (0.5 to 630m2)
Increase in focal length (7.5 to 50m)
Optics and focal imaging on
separate satellites
6% “out of time” events in XMM
Focal detector requirements:




faster readout (factor 10 to 100)
avoidance of ''out of time'' events
larger size focal detector (7x7cm2)
smaller pixel size (50•50μm2)
Detector requirements can be met with
DEPFET pixel detectors
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Present DEPFET pixel detector development for
XEUS and TESLA
In collaboration with Bonn (N.Wermes) and Mannheim (P.Fischer)
TESLA vertex detector
Thin
Fast
Low power
Total > 500 MPixel (with 25x25 µm Pixelsize)
(read out speed 50 MHz)
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Options:
CCD
MAPS
HAPS
DEPFET
Layer
Module size
No. Of
modules
I
13 x 100 mm
1x8
II
22 x 125 mm
2x8
III
22 x 125 mm
2 x 12
IV
22 x 125 mm
2 x 16
V
22 x 125 mm
2 x 20
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Design of DEPFET pixel detectors
Type of DEPFETS:
MOS-depletion type
XEUS: zylindrical geometry
TESLA: rectangular geometry
Technology:
6 Inch
Double-poly,
double metal,
Self-aligned
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DEPMOS Technology Simulation
DEPMOS pixel array cuts through one cell
Clear
Gclear
Channnel
Metal 2
Metal 2
Metal 1
Metal 1
Oxyd
Poly 2
Poly 1
Poly 2
n+
Deep p
Along the channel
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p
Deep n
Perpendicular to the channel
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Pixel prototype production (6“ wafer)
for XEUS and LC (TESLA)
Aim: Select design options for an optimized array operation
(no charge loss, high gain, low noise, good clear operation)
On base of these results => production of full size sensors
Many test arrays
- Circular and linear DEPFETS
up to 128 x 128 pixels
minimum pixel size about 30 x 30 µm²
- variety of special test structures
Structures requiring only one metalization layer
Production up to first metal layer finished
Devices are under test
Test results agree very well with
device simulations
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First DEPFET measurements
on rectangular test transistors
(W = 120µm L = 5µm)
Output characteristics:
Correct transistor behavior
Transfer characteristics:
Device can be completely
switched off
Transistor parameters
agree with simulation
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DEPFET test results: Noise and Spectroscopy
Single circular DEPFET
L = 5 µm, W = 40 µm
time-continuous filter, τ = 6 µsec
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Rectangular double cell test structure
as used in TESLA pixel prototype
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I (nach Clearpuls) in Abhängigkeit von dem Clear hi level
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DEPFET test results
Clearing of internal gate:
complete clearing possible?
At which voltage?
80
I lo [µA]
Single rectangular DEPFET:
100
60
measure current with
40
cleared internal gate
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As function of clear voltage
0
0
5
10
15
20
Clear hi level [V]
Breite der ADC-peaks 2ms nach dem Clearpuls
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Measure pedestal noise
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Compare situation of
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Single clear pulse
charge generation followed by
single clear pulse
with
many clear pulses
FWHM [ch]
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12
10
8
6
Many clear pulses
4
2
before reading
0
4
6
8
10
12
14
16
18
20
Clear hi level [V]
burst
single samples
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TESLA Module concept with DEPFETs
Auslesechips
520 x 4000 pixel
DEPFET-Matrix
(25 x 25µm Pixel)
Steuerchips
Auslesechips
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• Sensor area thinned down to 50 µm
• Remaining frame for mechanical stability
carrying readout and steering chips
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Module Concept
readout chips
Auslesechips
5-layer (CCD-like) layout for the vertex detector
1st layer module: sensitive area 100x13 mm2
sensitive area thinned down to 50 mm, supported by a directly
bonded 300 mm thick frame of silicon
520 x 4000 pixel
DEPFET-Matrix
(25 x 25µm Pixel)
Estimated Material Budget (1st layer):
Steuerchips
Pixel area:
100x13 mm2, 50 µm : 0.05% X0
steer. chips:
100x2 mm2, 50 µm : 0.008% X0
(massive) Frame :100x4 mm2, 300 µm : 0.09% X0
reduce frame material!!!
by
etching of "holes" in the frame
perforated frame: 0.05 % X0
Auslesechips
readout chips
total: 0.11 % X0
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Processing thin detectors
- the Idea a) oxidation and back side implant of top wafer
Top Wafer
c) process  passivation
Handle <100> Wafer
open backside passivation
b) wafer bonding and grinding/polishing of top wafer
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d) anisotropic deep etching opens "windows" in handle
wafer
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Processing thin detectors
- Direct Wafer Bonding “SOI” Wafer prepared by
MPI für Microstrukturphysik, Halle
Q.-Y. Tong and U. Gösele “ Semiconductor Wafer Bonding ”
John Wiley & Sons, Inc.
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picture from: www.mpi-halle.mpg.de
picture from: www.mpi-halle.mpg.de
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Direct Wafer bonding after Implantation
Bonded wafers (structured implant through BOX):
Direct Wafer Bonding possible, but some voids after annealing!
 improve surface condition before bonding
infrared transmission pictures from MPI Halle (M. Reiche)
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Anisotropic Wet Etching
- TMAH Tetra-Methyl-Ammonium-Hydroxide
good selectivity to oxide
almost perfect selectivity to Al
no alkali ions
poorer selectivity to (111) (≈30:1)
rough surface after etching (hillocks)
54.72 deg
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Diodes & Teststructures on thin Silicon
* test bondability of implanted oxide & electrical performance of diodes on thin silicon *
2 types of thinned diodes
Type I: Simplified standard technology
p+
guard ring
Type II: Implants like DEPFET config.
n+
SiO2
n+
SiO2
p+
Al
structured p+ on top
unstructured n+ in bond region
3 Wafers
Al
unstructured n+ on top
structured p+ in bond region
3 Wafers
* + 4 Wafers with standard Diodes as a reference *
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Diodes & Teststructures on thin Silicon
- Type I: CV curves, full depletion voltage -
50 µm, standard diode, 10 mm2
1/C2 (10-4 nF-2)
1/C2 (10-4 nF-2)
250 µm, standard diode, 10 mm2
bias voltage (V)
bias voltage (V)
C(Vfd)  t = 46 mm
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Diodes & Teststructures on thin Silicon
- Type I: IV curves -
250 µm, 4 standard diodes, 10 mm2
50 µm, 4 standard diodes, 10 mm2
800..950 pA/cm2
bias voltage (V)
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reverse current (pA)
reverse current (pA)
back side completely free
700..850 pA/cm2
bias voltage (V)
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Diodes & Teststructures on thin Silicon
- Type II: IV curves Diodes of various sizes: 0.09 cm2 – 6.5 cm2
- no guard ring - surface generated edge current included –
reverse currents after annealing
reverse current (nA)
contact opening and metallization
after etching of the handle wafer
bias voltage (V)
about 2V full depletion voltage
 about 1 nA/cm2 including edge generated current
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Readout electronics for DEPFET pixels
Developed in collaboration with other
groups:
•XEUS: MPE,Jülich,Buttler
•TESLA: Bonn, Mannheim,MPI
Auslesechips
520 x 4000 pixel
DEPFET-Matrix
(25 x 25µm Pixel)
Steuerchips
TESLA readout chip
Current based readout
Driver chips:
Switching
Clearing
Row selection
Auslesechips
Readout chips:
Signal amplification
Pedestal subtraction
Zero suppression
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New steering chip
I.Peric (Bonn), P.Fischer (Mannheim)
Switcher II:
• AMS 0.8µm HV
• versatile sequencing chip
(internal sequencer  flexible pattern)
• high speed + high voltage range (20V)
• drives 64 DEPFET-rows
(can be daisy chained)
• produced 12/2002
4.8 mm
4.6 mm
1
Results:
• power consumption:
~1W /channel
• tested ok to 30MHz
0
1
20ns
U = 20V
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 = 30 MHz
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Current based Readout
How to store a current ??
IBias
I In
input
ISTORE
output
sample
Storage phase: input and sample-switch closed :
 gate-capacitance of nmos charged
Sampling phase: input and sample-switch opened :
 voltage at capacitance „unchanged“
 current unchanged
I = I In + IBias
CGate
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Transfer phase: output switch closed :
(done immediately after sampling)
 ISTORE is flowing out
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CURO - Architecture
CURO : CUrrent Read Out
 front end:
automatic pedestal subtraction
(double correlated sampling)
- easy with currents  analog currents buffered in FIFO
 Hit-Logic performs 0 suppression
and multiplexes hits to ADC
(ADC only digitizes hits !)
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Results - CURO I
(Marcel Trimpl, Bonn)
CURO I:
1.5 mm
 TSMC 0.25µm, 5metal
 contains all blocks for a fast DEPFET R/O
 radiation tolerant layout rules with annular nmos
 produced 05/2002
digital part:
works with desired speed (50MHz)
4 mm
analog part (current memory cell):
• tested up to: 25MHz
• differential non-linearity: 0.1 %
• noise contribution to readout: < 39nA
70
Measured linearity
of memory cell
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Ioutput [µA]
50
40
Crucial parts of readout work
Design of CURO II submitted
Delivery Dec.03
30
20
10
IBias= 70µA
0
0
10
20
30
40
50
60
70
TESLA Goal:
Thin fullsize pixel matrix 2005
Iinput [µA]
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Summary
DEPFET structure invented 1984
Offers many unique features and applications
Development in MPI Semiconductor Detector Laboratory
• with high-tech production technology
• in collaboration with other institutes
DEPFET pixel detectors for
 X-ray astronomy (XEUS)
 Particle physics (TESLA)
are major projects of the laboratory
Other applications are also foreseen
Development is progressing very well
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