Transcript MAPS - Institut Pluridisciplinaire Hubert Curien

 SLIM - MimoTERA – chip design
MimoTera:
 Combination of detection thinning
and microelectronics,
 AMS CUA 0.6 µm CMOS process
with 14 µm epitaxial layer –
(MIMOSA V),
28 columns
(30 clocks)
17.136×17.136 mm2
 Chip prepared for back-thinning
Subarray 3
 Respected pad positions from
MIMOSA V; but larger size 85×185
µm2 (bonding),
Subarray 2
 Four sub-arrays of 28×112 pixels
read out in parallel tread/integr<100µs,
no dead time – alternate integration
and readout in halves of pixels,
Subarray 1
 Total array of 112×112 153×153µm2
square pixels, each pixel –
interdigited array of small n-well/pepi diodes,
Subarray 0
 Chip size: 17350×19607µm2,
112 rows
(114 clocks)
digital
 delivery expected ~15th of January 2005
 SLIM - MimoTERA – chip design
MimoTera:
 Two 9×9 interdigited arrays of
n-well/p-epi diodes (5×5 µm2)
with two independent FE
electronics,
 No dead time in pixel
operation – alternate reset and
integration in both arrays,
 In-pixel storage capacitors –
choice ~0.5pF or ~5pF to cope
with signal range,
 Readout without CDS – kTC
noise,
 Signal swing ~2 V (pixel and
chip output) @ 40Mpixel/s,
 CVF=~250nV/e- @ 500fF; noise ~1000 e-  280 e- kTC (ENC) @ 500fF
 SLIM - MimoTERA – chip design
Pixel
schematic
diagram
Half B
Switch to vdda
to cut
consumption
when line
precharging
Half A
 SLIM - MimoTERA – chip design
 1 chip quarter architecture
4×
 SLIM - MimoTERA – chip design
Column
level
circuit
column
input
Half A
precharging
to vdd voltage before
each readout to  speed
Half B
precharging
to low voltage before
each readout to  speed
current source OFF
current source OFF
horizontal line
to 3:1 MUX
 SLIM - MimoTERA – chip design
Array output circuit
horizontal lines (3)
4.3 mm
MUX buffers
external
voltage reference
3:1 MUX for 3 phase
column readout with
increased time for line
charging
current bias
generated internally
D/A Convertor
reconfigurable gain
output amplifier
gain: ×1 or ×5