Transcript ppt - UCSB HEP - University of California, Santa Barbara

The BaBar Silicon Vertex
Tracker (SVT)
Claudio Campagnari
University of California
1
Santa Barbara
Outline
• Requirements
• Detector Description
• Performance
• Radiation
2
SVT Design Requirements (TDR)
Performance Requirements
• Dz resolution < 130 mm
• Single vertex resolution < 80 mm.
• Stand-alone tracking for PT < 100 MeV/c.
PEP-II Constraints
• Permanent dipole (B1) magnets at +/- 20 cm from IP.
• Polar angle restriction: 17.20 < Q < 1500.
• Must be clam-shelled into place after installation of B1 magnets
• Bunch crossing period: 4.2 ns (nearly continuous interactions).
• Radiation exposure at innermost layer (nominal background level):
• Average:
33 kRad/year.
• In beam plane:
240 kRad/year.
• SVT is designed to function in up to 10 X nominal background.
3
SVT characteristics
• Five layers, double sided (R and z)
– Barrel design, L4 and 5 not cylindrical
– 340 wafers, 6 different types
– Low mass Kevlar-Carbon Fiber support ribs
• Upilex fanouts to route signal to ends
• Double-sided AlN HDI (104 of these)
– Outside tracking volume
– Mounted on Carbon Fiber cones (on B1
magnets)
• Atom chips
– 1156 chips, 140K channels
4
Space Frame and Support
Cones…mounted on B1 magnets
5
Layer
Radius
(mm)
Modules/
Layer
Wafers/
Module
Pitch
mm)
Z Pitch
mm)
1
2
3
32
40
54
6
6
6
4
4
6
50 or 100
55 or 110
55 or 110
100
100
100
4a
124
8
7
100
210
4b
127
8
7
100
210
5a
140
9
8
100
210
5b
144
9
8
100
210
Layer 1,2,(3): vertexing
Layer (3),4,5: tracking
6
SVT Modules
Z-Side
High Density
Interconnect
(mechanical model)
Micro-bonds
Flexible Upilex Fanout
Micro-bonds
Phi-Side
Fanout Properties:
• < 0.03 % X0
• 0.52 pF/cm
Si Wafers
Carbon/Kevlar fiber
Support ribs
7
SVT High Density Interconnect
Functions:
• Mounting and cooling
for readout ICs.
• Mechanical mounting point
for module.
Features:
• AlN substrate.
• Double sided.
• Thermistor for temp. monitor.
• 3 different models.
Flexible Tail (testing version)
Berg
Connector
Mounting
Buttons
AToM
Chips
Upilex
Fanout
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Silicon Wafers
Features
•Manufactured at Micron.
•300 mm thick.
•6 different wafer designs.
•n- bulk, 4-8 kWcm.
•AC coupling to strip implants.
•Polysilicon Bias resistors on wafer, 5 MW.
Bulk Properties
• Bias current: 0.1 to 2.0 mA
• Bulk current: 0.1 to 2.0 mA
• Depletion voltage: 10 to 45 V
Strip Properties
n-side
n-side
n-side
p-side
• Strip Pitch:
50 mm
55 mm
105 mm
50 mm
• Inter-strip C:
1.1 pF/cm
1.0 pF/cm
1.0 pF/cm
1.1 pF/cm
• AC decoupling C:
20 pF/cm
22 pF/cm
34 pF/cm
43 pF/cm
0.19 pF/cm
0.36 pF/cm
0.17 pF/cm
4 to 8 MW
4 to 8 MW
4 to 8 MW
• Implant-to-back C:
• Bias R:
4 to 8 MW
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Silicon Wafers
Edge
guard ring
Bias ring
Polysilicon
bias resistor
P-stop
55 mm
n+ Implant
p+ Implant
Al
50 mm
Polysilicon
bias resistor
p+ strip side
Edge
guard ring
n+ strip side
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The AToM Chip
Custom Si readout IC
AToM = A Time Over threshold Machine
8.3 mm
Features:
•128 Channels per chip
•Rad-Hard CMOS process (Honeywell)
•Simultaneous
– Acquisition
– Digitization
– Readout
•Sparsified readout
•Time Over Threshold (TOT) readout
•Internal charge injection
5.7 mm
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The AToM Chip
Si
15 MHz
PRE
AMP
Shaper
CAL DAC
Comp
Thresh
DAC
CINJ
Revolving
Buffer
193 Bins
TOT Counter
Time Stamp
Buffer
Event Time
Event Number
Buffer
Sparsification
Readout Buffer
Chan #
CAC
Serial
Data Out
Amp, Shape, Discr, Calib
•5-bit CAL DAC (0.5 fC/count)
•5-bit Thr DAC (0.05 fC/count)
•Shaping time 100 - 400 ns
•Typical threshold 0.6-0.9 fC
Trigger Latency Buffer
•15 MHz Sample rate
•Total storage = 12.7 us
TOT, Tstamp, Buffering
•4 bits TOT (logarithmic)
•5 bits Hit Tstamp
(67 ns/count)
•4 buffers / channel
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Performance
•
•
•
•
Calibration, Noise
Occupancy
Efficiency
Intrinsic Resolution
13
• Noise, gain, pedestals, bad channels
obtained from scanning threshold
with and without charge injection
and counting hits
Hits
Calibration
Noise
– 600K errfun fits, 150K linear fits
– once a day; takes ~ 2 minutes
– needed to change because of rad
damage
Offset
Threshold
Offset Counts
• Very stable
• Downloadable chip parameters have
not changed between Oct 1999 and
~ 2004
Threshold DAC
Offset
Qinj Counts
14
Alignment: a curiosity
• SVT tied to machine elements, not to DCH
• SVT is always moving w.r.t. BaBar due to e.g.
thermal excursions.
• Position of SVT as rigid body is monitored and
fed back to reconstruction ~ every hour
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Noise
Layer ENC
Layer ENC
1
1200
1z
880
2
1240
2z
970
3
1440
3z
1180
4
1350
4z
1210
5
1600
5z
1200
1 MIP at normal incidence, about 23,000 electrons
16
Cluster efficiency
e~97%
(SW + HW)
Excluding malfunctioning
readout sections
17
Resolution
Blue: data
Red: MC
18
Standalone reconstruction
of low PT tracks
Reconstruction of ps from
D*  D ps
is (mostly) with SVT alone
19
Most of the detector is working
• Redundancy built in, e.g., 2 data and control paths
• Chips are only active electronics that is not accessible
• Layer 1 perfect
• 4/208 sections not working
• Problems are from
• shorts on hybrids
• elec. probems on wafers
short
2 chips
masked
short
Both noisy
20
Radiation
• Monitored by 12 diodes
at ~ radius of layer 1
• Diodes can abort beam
• Operation tricky due to
heavy radiation damage
• Now also use diamonds
SVTRAD System
21
Measured absorbed Dose
non-midplane
midplane
Few MRad in the horizontal plane
Mostly from showers from
off-momentum beam particles
Not from Physics
22
Consequences of high doses
• Bulk damage to Si
– increase ILEAK  increase in noise
– type inversion
• Damage to chips
– originally tested to 5 MRad with Co
source
23
~ Damage effectiveness 
Bulk Damage
from Moll
NIEL scaling: high energy electron cause
significant damage (~1/10 of hadrons)
Not appreciated by us originally
24
Tests at Elettra (Trieste)
• C-2 vs V curve show inversion
• Results in ~ agreement with
NIEL scaling hypothesis
• Charge-collection-efficiency after
local type inversion measured: OK
25
Expected Atom Chip Damage
Radiation damage on AToM chip
• studied using Co60 sources at LBL
and SLAC, up to 5 MRad.
• No digital failures (if chip power on)
• Gain loss 4.2% / MRad
• Noise increase: 19%/MRad
26
Unexpected Phenomenon: Pedestal Shift
• Pedestal (Threshold offset) started to increase
• Behavior associated with AToM chip location, not
with strip location
• Remember: we have 1 pedestal value per chip!!!
Threshold offset (counts)
Pedestal
HDI Card in horizontal plane
Chip 4
Channel
20 threshold DACs = 1fC
27
Sets in at an integrated radiation dose of 1 Mrad
But then it recovers.
Effect reproduced at Elettra
Ride out the storm by adjusting thresholds as well as
we can
AToM Chip
narrow e- beam
2 Mrad
1 Mrad
Groups of 8 channels
Delta Threshold (counts)
Threshold offset (counts)
•
•
•
•
Pedestal Shift (cont.)
Integrated Radiation
Pedestal recovers
Effect reproduced @ Elettra
Channel
28
Unexpected Phenomenon:
Leakage Current Increase
Apr
May
Jun
ILeak (mA)
300uA
10uA
Days in 2004
• Since May 2004 an anomalous
increase in the bias current
for some modules has been
observed
• Only Layer-4 modules:
not a simple radiation damage
effect
• No geometrical correlation
• Consequences:
increasing occupancies
• Coincides with beginning of
"trickle injection" operation
– beam always on!!!!!
29
Leakage Current Increase
-20V
+20V
-20V
E
+20V
Hypothesis:
Accumulation of static charge on the silicon
surface. The charge is beam-induced drifts
because of the field between the facing sides
of different layers.
Causes increase in electric field at junction
edge, inducing a soft junction breakdown.
ILeak (mA)
DVL5-L4=+40V
By varying the potential drop
across the air between the
layers we can control the
effect
Solution: change relative voltages, L4 vs L5
Also, increase humidity of air
1800
0000
0600
1200
Time (hrs)
30
Conclusions
• BaBar SVT has been working well for
about 7 years now
– Installed and cabled in April 99
– Taking physics quality data since June 99
• There have been a few surprises along
the way, but we have managed to survive
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