Transcript Document

Review of Vertex Detector R&D
for International Linear Collider
• ILC
• Vertex Detector R&D
- CCD (ISSI)
- MAPS
- DEPFET
• Summary
Jik Lee
Seoul National Univ.
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International Linear Collider
 electron and positron linear collider
at energy from 500 GeV up to 1 TeV
and electron beam polarization > 80%
and upgrade option for positron polarization
 Accelerator technology chosen: cold
 3 Projects at
- DESY (TeV Energy Superconducting Linear Accelerator)
DESY
- Japan (Global Linear Collider)
SLAC
CERN
- US (Next Linear Collider)
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KEK
▣ ILC Detectors
Main Tracker drives ILC detector configurations
Gaseous Tracker
Silicon Tracker
5 tesla
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Medium/Large
4 tesla
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Large/Huge
3 tesla
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ILC Environment for
Vertex Detector
• Silicon based vertex detector(s):
CCD, MAPS, DEPFET, and more
- 4-5 cylindrical layers
able to do stand alone tracking
- background tolerance
- fast (due to problem of overlapping events)
SVD in SD design
Beam Structures
Warm
Cold
bunch/train
192
2820
train length
269 ns
950 µs
bunch spacing
1.4 ns
337 ns
150/120 Hz
5 Hz
train/s
gap/train
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6.6 ms
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ILC Vertex Detector Requirements
• Close to IP  reduce extrapolation error
• Pixel Size:20x20mm2  sPoint =3 mm : ~800M channels
• Layer Thickness: <0.1%X0
suppression of g conversions
minimize multiple scattering
LC environment requires vertex sensors which are substantially thinner and
more precise than LHC and thus motivates new directions for R&D on
vertex sensors:
1/5 rbp, 1/30 pixel size, 1/3 thinner than LHC sensors
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Vertex Detector R&D Groups
CCD
LCFI (Bristol, Glasgow, Lancaster, Liverpool, Oxford, RAL) : UK
Niigata, KEK, Tohoku, Toyama : Japan
Oregon, Yale, SLAC : US
MAPS
Strasbourg (IReS, LEPSI) + DAPNIA+DESY :
France + Russia+Germany
Brunel, Birmingham, CCLRC, Glasgow, Liverpool, RAL : UK
DEPFET
Bonn,MPI : Germany
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Vertex Detector Comparison
Do not take this seriously.
It could be wrong due to my personal bias and ignorance!
CCD MAPS DEPFET
Resolution
Thin Material
Rad. Hardness
Large Area
Power Consum.
Readout speed
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CCD (Charge Coupled Device)
▪ charge collected in thin layer
and transferred through silicon
▪ established technology
▪ excellent experience at SLD in SLC
300µm
 40µm
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• ~ 20 x 20 µm2 pixels  800 M pixels
- SLD: 300 M pixels
• coordinate precision: 2-5 µm
- SLD: 4 µm
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CCD Basics
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CCD Basics
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CCD ISSUES
CCD classic
▪ faster readout needed for cold tech (50 µs)
• Column-Parallel CCD with low noise
- increase readout cycle of ~50MHz
CP CCD
▪ need radiation hard 
separate
amplifier and
readout for
each column
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• bulk damage induced CTI by n and e- being
actively studied with possible countermeasures
- sacrificial charge, faster r/o before trapping
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CCD Prototype (LCFI)
CPC1: prototype CP CCD by E2V
noise ~ 100 eCPR1: CP readout ASIC by RAL
designed for 50 MHz
250 parallel channels
750 x 400 pixels
CPC1+CPR1(bump-bonded):
total noise ~ 140 enoise from preamps negligible
20 mm pitch
CPR1
CPR1
noise
• radiation effects on fast CCDs
• detector-scale CCDs with ASIC and cluster finding logic
- design underway and production this year
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5.9 keV(1620e-)
Signal from a 55Fe source observed
CCD Radiation Study (KEK))
LED light makes sacrificial charge
in CCD. It fills up traps and improve
CTI
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VCTI is improved to a half of normal operation
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CCD Summary
• performance proven at SLD
• good spacial resolution ( < 5µm)
• improve slow readout speed  50 MHz CP readout
• improve the radiation hardness  charge injection, notch structure
• material reduction with unsupported silicon
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Image Sensor with In-situ Storage (ISIS)
• 20 readouts/bunch train may be impossible
due to beam –related RF pick up
 motivates delayed operation of detector for
long bunch train:
• charge collection to photogate from 20-30 µm
silicon, as in a conventional CCD
• signal charge shifted into storage register
every 50 µs, providing required time slicing
• string of signal charges is stored during bunch
train in a buried channel, avoiding chargevoltage conversion
• totally noise-free charge storage, ready for
readout in 200 ms of calm conditions between
trains
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Monolithic Active Pixel Sensors
• standard CMOS wafer
• charge collection via
thermal diffusion (no HV)
in epitaxial layer
•“System on Chip” possible
• NO bump bonding
~10-20µm
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APS2 chip (UK)
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3MOS
des. A
Row decoder/control
• 4 pixel types, various flavours
• Std 3MOS
[3T]
• 4MOS (CDS)
[4T]
• CPA (charge amp)
• FAPS (10 deep pipeline)
• 3MOS and 4MOS: 64 x 64,
15mm pitch, 8mm epi-layer
 MIP signal ~600 e-
3MOS
des. B
3MOS
des. C
3MOS
des. D
3MOS
des. E
4MOS
des. A
FAPS
CPA des. A
4MOS des. A
FAPS
des. B
des. B
4MOS CPA
des. C des. B FAPS
des. C
4MOS
des. D CPA
FAPS
des.
C
4MOS
des. D
des. E
4MOS CPA FAPS
des. F des. D des. E
3MOS
des. F
Column
amplifiers
Column decoder/control
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J. Lee
5.8 mm
Design: R. Turchetta (RAL)
Radioactive source Tests on APS2 structures
• seed pixel
• 3x3 cluster
• 5x5 cluster
Event display
spectrum
• Out of 12 substructures 7 feature a S/N > 20
• Two structures problems in fabrication
• Bad pixels: 1-2%
• Preliminary results on irradiation up to 1015 p/cm2 promising
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Mimosa prototypes (France)
CHIP
YEAR
PROCESS
EPITAXIAL
PITCH
mm
mm
METAL
PECULIAR
M1
1999
AMS 0.6 mm
14
20
3M
thick epitaxy
M2
2000
MIETEC 0.35 mm
4,2
20
5M
thin epitaxy
M3
2001
IBM 0.25 mm
2
8
3M
deep sub-mm
M4
2001
AMS 0.35 mm
0!
20
3M
low dop. Substrate
SUC 2
2003
AMS 0.35 mm
none
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3M
low dop. Substrate (SUCIMA project)
M5 & M5B
2001/2003
AMS 0.6 mm
14
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3M
real scale 1M pixels
M6
2002
MIETEC 0.35 mm
4,2
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5M
col. // r.o. and integrated spars.
M7
M8
M9
SUC 1
2003
2003
2004
AMS 0.35 mm
TSMC 0.25 mm
AMS 0.35 m
none
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20
25
25
20/30/40
4M
5M
4M
col. // r.o. and integ. spars. (photoFET)
col. // r.o. and integrated spars.
opto. tests diodes/pitch/leakage current.
irradiation tests
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MIMOSA-9
MIMOSA-9: 20,30,40 µm pitch
with/without 20µm epi. layer
Self-Bias, Pitch = 20 mm, diode 6 x 6 mm2
Tested at CERN SPS-120 GeV pion beam
0.1% X0 layer is achievable in
thinning to 50µm:
- Sensor back-thinned to 15µm
S/N peak~24
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MIMOSA-9 Results
SB with 20/30 mm pitch :
eff ≥ 99.8%
resolution ~ 1.5 mm @ 20 mm pitch
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A promising result
since a high eff and
a good resolution
for a moderate granularity
can not be for granted.
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MAPS Radiation Tolerance
• neutron irradiations
- fluencies up to 1012 neutrons/cm2 are
acceptable with considering
LC requirements of ~ 109 n/ cm2 /year
• ionizing irradiations
- tests up to a few 100kRad
- exact sources of performance losses are
under investigation (diode size and
placements of the transistors are important
parameters)
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MAPS Summary
• readout and sensor on one chip
• pixel size ~ CCD
• large area sensor and thinning (MIMOSA-9 tested OK)
  > 99%, 20 µm pitch  s ~ 2µm
• reasonable radiation hardness
• fast readout (50 MHz possible, MIMOSA6:currently CDS takes time)
• R&D required to bring layer thickness down
• Optimize architecture for LC
 Flexible APS (FAPS) architecture suitable for LC and
fast imaging
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FAPS
The in-pixel amp accesses the
“Out” line, which is connected to
all the pixels in a column
 Relatively large capacitive load (>~pF)
 Relatively slow
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The in-pixel amp accesses
only local storage capacitors
Small capacitive load (<<pF)
Write and read phase saparate
 Fast
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FAPS Design (RAL)
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DEPleted Field Effect Transistor Sensors
DEPFET: detector + amplification property
mip
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- high resistivity silicon substrate
- fully depleted by sidewards depletion
 full sensitivity over whole bulk
- electrons collected in internal gate and modulate
transistor current
- internal gate can be reset by applying voltage to
a dedicated contact
 no reset noise
- the first amplifying transistors are integrated
directly into substrate and form pixel structure
 a small input capacitance (~ 10fF)
 very low noise operation can be achieved
at room temp. (10 e-)
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DEPFET
• DEPFET collaboration: Bonn/MPI
MIP
source top gate drain
n+
p+
~1µm
p+
clear
bulk
n+
n+
• p-channel MOS-FETs
• double pixel structure
(one source two drains)
• pixel size 20x25µm2
n
- -+ gate
-- internal
-+
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50 µm
symmetry axis
p
n-
p+
rear contact
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▪ detector and amplification properties
▪ fully sensitivity over whole bulk
▪ very low noise operation at room temp.
▪ readout speed ?
▪ radiation hardness ?
▪ large-area sensor?
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DEPFET Performance
Excellent noise performance with 55Fe source spectrum
Single pixel
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Result at Room Temperature:
 131 eV @ 5.9 keV
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2.2 el. r.m.s.
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▣ Vertex Detector: DEPFET Prototype
• thinning process for sensors established
- sensitive area 50µm thinned
- fast signal to cope with
high rate requirement
- resolution of 9.5 µm
800x104 mm2
• complete clear  no clear noise
- (1 x clear) then sample 500x in 2.5ms
- (clear + sample) 500x
for single pixel
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DEPFET Readout
Reset
Switcher
Gate
Switcher
• system integration of
a 64x128 pixel matrix
o steering chip (Switchers) tested
up to 80 MHz
o the read-out chip (the CURO) works
up to 50/110 MHz (A/D): noise & threshold
dispersion meets the specs
• prototype system with DEPFET + CMOS
matrix is assembled and working
I→U
CURO II
ADCs
• designing and producing a 512 x 512 matrix
is planned
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row wise
selection with
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Switcher
XILINX
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DEPFET Summary
• excellent low noise performance at room temperature
• low power consumption (saving material for cooling
structure)
• readout speed increasing
• possibilities of thinning the sensor (20-30 μm)
and readout chip
• minimize pixel size
• radiation hardness
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Vertex Detector Comparison Now
Do not take this seriously.
It could be wrong due to my bias and ignorance!
CCD MAPS DEPFET
Resolution
Thin Material
Rad. Hardness
Large Area
Power Consum.
Readout speed
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Summary
• Intensive R&D in several VTX technologies
with good world-wide communication going on!
• Premature choice of technology could seriously
degrade the physics potential
• Preferred technology(ies) to be selected
on basis of full-size and fully operational prototype ladders
(when?)
▪ Time Scale
2004 Cold technology chosen
2005 CDR for ILC (including first cost estimation)
2007 TDR for ILC
2008 site selection
2009 construction could start
2015 data
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backups
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DEPFET Operation Mode
Pixel array readout scheme:
Individual transistors or
rows of transistors can be
selected for readout while the
other transistors are turned off.
Those are still able to collect
signal charge
fast random access to specific
array regions
 very low power consumption
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Overview: R/O Chip - CURO
CURO – CUrrent ReadOut
Spalte i
current based readout
→ regulated cascode fixes input node
• algebraic operations easy in current mode !
cascode
Isig
Iped + Isig
current
buffer A
current
buffer B
1/0
pedestal
sub.
current
FIFO
cells
• automatic pedestal subtraction (fast CDS)
• „on chip“ hit detection and zero suppression
current
compare
Isig
outA
2x Output-MUX
outB
• analog r/o of hits
Hit-Finder
hit
HIT-FIFO
hit-address: rowstamp, column
serial-out
CURO I: prototype chip
(05/2002)
Main parts :
• current memory cells
• current comparator
• hit finder
CURO II: 128 channel r/o chip
(11/2003)
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