Transcript We choose Xilinx (Virtex V family, with hard PCIe core)

PCIe Mezzanine Carrier
Pablo Alvarez
BE/CO
Functional Specifications
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External Interfaces
User (application) FPGA
System FPGA
Memory blocks
Mezzanine
Test capabilities
Monitoring
Technical Details
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FPGA (Xilinx vs Altera)
Power supplies
Functional Specifications
-External Interfaces-
• 1 Lane PCIe 200MB/s
• White Rabbit capable Ethernet
connection via a SFP socket to
support electrical and optical media
Functional Specifications
-System FPGA•
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Load Aplication FPGA bitstream
Immediate access to PCIe SMBus
Monitoring of the board temperature
Access to a unique PCB ID identification
Access to PCB and Firmware Version Identification
Readout of the Mezzanine Version Identification
Status (configuration) of the Application FPGA
Access to Power Monitor
Functional Specifications
-Application FPGA•
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At least twice the logic elements of an Altera EP1S40 (validated via cross synthesis
of an existing project)
Direct connection to the mezzanine connector
Direct access to 2 independent SRAM blocks and DRAM
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Direct access to PCIe
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Direct access to Ethernet
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Basic startup libraries for the firmware development (System FPGA communication
blocks)
Possibility of remote configuration of the application FPGA FLASH via PCIe, SMBus,
Ethernet and JTAG connector
Functional Specifications
-Memory Blocks•
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Two independent ZBT SRAM blocks 36x512 (18
Mb each)
DRAM block (SO DIMM?)
EEPROM capable of storing at least 2
configuration files for the application FPGA
Functional Specifications
-Test Capabilities•
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Scan bridge mastered via PCIe JTAG pins or
lateral JTAG connector
Dedicated Mezzanine JTAG chain
System and Application FPGA on the same JTAG
chain
Dedicated FLASH JTAG chain
Functional Specifications
-Monitoring-
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Temperature monitor on FPGA and under Mezzanine
Current and Voltage monitor on Power supplies
JTAG
Conn1
6 diff IOs
Conn2
6 diff IOs
1 Lane PCIe
Slot
12V
12V/3V3
DC/D
C
2V5
VADJ (0-3V3)
3V3
1V8
PCIe 250MB/s
ZBT SRAM 2
SO DIMM module
Ethernet
Phy + WR
Mac
FMC connectors
ZBT SRAM 1
PCIe
Phy+
Mac
Application
(User)
FPGA
Individual ID
PCB ID
Individual ID
Mez ID
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I2C
Flash
Partition #0
Partition #1
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Configuration
Watchdog+
Monitoring
I2C
SFP
socket
Technical Implementation Details
Altera or Xilinx?
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User IOs connected to the mezzanine should be fully configurable.
In general all Xilinx’s IOs support Digital Controlled Impedance (DCI) for
all IOs standards
In Altera’s FPGA’s aproximately half of the IOs in a bank support
LVDS Input On-Chip Termination
 Half of the pins of the banks connected to the
Mezannine would be unused in an Altera (ArriaIIGX or
Stratix IV)
We choose Xilinx (Virtex V family, with hard PCIe core)
Technical Implementation Details
-FPGA 2•
Aplication FPGA: Virtex 5 FF665 Package—LX30T(300$),
FX30T, LX50T, SX35T, SX50T (800$), and FX70T(1200$)
Technical Implementation Details
Powering
•At least 25W required
•Impossible to meet specs on accuracy for 12V
•3V3 for the mezzanine should also be generated from the 12V
•Is it really necessary to add special power supplies to the
Mezzanine connector??