Transcript Achronix Semiconductor Corporation Venture Overview

The World’s Fastest CMOS FPGA for Commercial and
Extreme Environments
Achronix Technology and Product Overview
Presented: November 15, 2005 – NASA Goddard Space Flight Center
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1
Agenda
Company Overview
Overview of Asynchronous Circuits
Achronix Technology & Solution Overview
Product Architecture and Specifications
2
Achronix Semiconductor Overview
History
Founded 2004 in Ithaca, NY
Founders include original
developers of technology at
Cornell Univ. - Dr. Rajit Manohar,
Dr. Clinton Kelly, IV, Dr. Virantha
Ekanayake - and John Lofton Holt
All founders except Dr.
Ekanayake are full time employees
of Achronix presently
Financed with owners capital to
date. Company is currently
working with several private
equity groups to fund production
in 2006.
Product Space
We make the world’s fastest
Field Programmable Gate Arrays
(FPGAs) in two product lines:
– Achronix-ULTRA: GHz
Speed Ultra high performance
FPGA
– Achronix-XTREME: GHz
Speed Extreme environment
(temperature and radiation)
FPGA
Status and Goals
Completed first successful
prototype of product in early 2005,
a 674 MHz FPGA fabricated in
TSMC 180nm CMOS
Completed second prototype in
October 2005 (due back in January
2006), a 1+GHz FPGA fabricated in
ST Microelectronics 90nm CMOS
Goal:
Competitors:
– FPGA Vendors: Xilinx,
Altera, Actel, Lattice, etc.
– Ship first product in 2006
– Achieve profitability in 2007
– ASIC Vendors: LSI Logic,
Fujitsu, IBM, Hitachi
Achronix’ technology is based on asynchronous logic
3
Our goal is to build GHz-speed FPGAs for commercial and extreme environments
Achronix Key Goals
Ultra fast Speed
– Support system throughputs in the 1+GHz (2006) to 2.5 GHz (2008) range through our asynchronous FPGA
fabric
Competitive Density and Power Performance
– While operating at GHz speeds, provide competitive density and power performance to state of the art
devices from Xilinx, Altera, Actel, and Lattice
Synchronicity and Interoperability
– At the system level, look and feel just like a traditional synchronous FPGA from Xilinx, Altera, Actel, Lattice,
and others by surrounding our fabric with traditional synchronous I/Os
Support the Existing EDA Landscape
– Support existing EDA tools used by FPGA and ASIC designers to ensure that our products can be integrated
easily and immediately and replace slower parts from or competitors
*Source: Simulations of Achronix 90nm design. Real results to be determined in January 2006
4
Agenda
Company Overview
Overview of Asynchronous Circuits
Achronix Technology & Solution Overview
Product Architecture and Specifications
5
Asynchronous circuits are not new in the research community or in the commercial world
First theory of an
asynchronous
computational machine
(Princeton)
1946 … 1969 … … … 1989
Introduction of
first commercial
RS232
asynchronous
serial interface
(Bell)
Fabrication of first
asynchronous
microprocessor
(Caltech)
Fabrication of fastest
asynchronous
microprocessor (Caltech)
1998
Introduction of first
asynchronous
commercial product
(Fulcrum Microsystems)
Design of first GHz
asynchronous FPGA
(Achronix)
Introduction of fastest
reconfigurable logic
module in CMOS
(Cornell
University/Achronix)
2003
2004
Introduction of first
microprocessor for sensor
networks (Cornell
University/Achronix)
2005
Introduction of asynchronous
interface logic in next
generation Itanium processor
(Intel)
*Source: A.W. Burks, H.H. Goldstein, and John von Neumann. Preliminary discussion of, the logical design of an electronic computing instrument. Institute for Advanced, Study, Princeton, N.J., June 1946., Wikipedia “RS232”, Manohar “The Impact of Ascynchrony on Computer
Architecture”, 1998, Naffziger, et al, “The Implementation of a 2-CoreMulti-Threaded Itanium Family Architecture”, ISSCC 2005
6
Asynchronous circuits operate in a fundamentally different way that their traditional
synchronous counterparts
Traditional Synchronous Circuit Behavior:
Discrete Time, Discrete Voltage
Asynchronous Circuit Behavior:
Continuous Time, Continuous Voltage
Clock
DATA 1
Sender
DATA
Receiver
Sender
DATA 0
Receiver
ACK
DATA “1”
DATA “1”
DATA “0”
DATA “0”
CLK
ACK
7
This asynchronous method of operation allows computations to be “pipelined”, which
reduces the complexity of operations, and facilitates more efficient parallel computation
c:= h(g(f(x)))
a:= f(x)
b:= g(a)
c:= h(b)
Synchronous Computation
Asynchronous Computation
The result: Faster execution, no registers required to store values, no power wasted
waiting for previous instructions to complete
8
The asynchronous approach has numerous advantages over traditional synchronous
circuits, and significant advantages in extreme environments, but there are challenges
Asynchronous Advantages
Speed: Circuit speed is no longer limited by a
clock
Power: Because circuits only operate when
they need to, standby power is dramatically
reduced and operating power is highly optimized
Redundancy: Data is encoded, therefore
redundancy can be exploited to locate permanent
faults and tolerate transient faults
Scaling: Circuits scale more efficiently as there
are not clock distribution issues and NO GLOBAL
SIGNALS (As the circuits scale, density increases
versus synchronous counterparts)
Asynchronous Challenges
Density: Increased number of wires for logic
functionality results in small area penalty in
individual circuits (mitigated by lack of clock
distribution logic required)
Synchronous Interfaces: The world of
electronics is synchronous, so asynchronous
systems must have synchronous “edges” to
interoperate with other synchronous devices in a
system
Delay Insensitive: Circuits do not depend on,
or make assumptions about delays.
The Achronix solution leverages the benefits while addressing the challenges to present a
product that can be used by customers today, using their existing designs and infrastructure
9
Agenda
Company Overview
Overview of Asynchronous Circuits
Achronix Technology & Solution Overview
Product Architecture and Specifications
10
Achronix has already built a 180nm prototype that operates at 674MHz system throughput,
over twice as fast as similar devices from FPGA industry leaders
180nm Prototype Layout
180nm Prototype Performance
180nm Prototype Die Photograph
Measured System Throughput (MHz)
Measured Performance - 180nm Prototype FPGA
1200
1000
800
T=-196C
600
T=21C
T=127C
400
200
0
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
2.1
2.2
2.3
Operating Voltage (Nominal = 1.8V)
90nm 1.8V Xilinx Virtex-4
maximum internal clock
speed (system throughput
significantly lower)
130nm 1.8V Xilinx Virtex-2
maximum internal clock
speed (system throughput
significantly lower)
Source: Xilinx Virtex-II and Virtex-4 data sheets. “Twice as fast” is conservative considering system throughput of Achronix device versus maximum throughput (25% - 80%of internal clock speed) of Xilinx devices.
180nm Achronix Measured
system throughput of 674
MHz at room temperature at
nominal operating voltage
of 1.8V
11
The 90nm prototype (October 2005) will operate at 1+GHZ speeds at lower power and
comparable densities as state-of-the-art FPGAs from Xilinx, Altera, Actel, and others
Speed - Achronix measured in System Throughput, Others measured
in Maximum Internal Clock Speed
No need to
migrate to
these
processes
now – Maybe
ever
3500
3000
2500
Internal Clock
2000
Speed (MHz.,
1500
Stated)
1000
32nm (2013)
45nm (2010)
65nm (2007)
Measured
674MHz with
180nm
prototype
90nm
Achronix FPGA
0
130nm
ASIC Speed
Speed:
– 180nm prototype: 674 MHz (measured)
– 90nm test chip: 1.4 - 1.6 GHz (Jan 2006)
Power (based on 180nm prototype):
– Consumes the same amount of power as a
conventional FPGA operating at 33%the
speed (Two thirds less energy per cycle)
500
180nm
FPGA Speed
Achronix Performance
Simulated for
90nm test chip
layout (due back
from Fab in Jan
06)
Density (based on 180nm prototype):
– Competitive with existing state-of-the-art
devices from industry leaders
– Will be monotonically higher in 90nm test
chip
*Source: SOCCentral.com Datasheet archive and Xilinx, Altera, Actel, Lattice Datasheets. Power not compared because reliable metrics unavailable, trends likely to mimic speed and density, 45nm and 32nm figures estimated based on trend analysis Years
expected for 65,45,and 32nm processes courtesy of “ITRS Roadmap for Semiconductors 2004”
12
We believe that these levels of speed will be unmatched by Xilinx, Altera, Actel, Lattice,
and even most ASIC vendors regardless of which fabrication processes are used
Speed - Achronix m easured in System
Throughput, Others m easured in Maxim um
Internal Clock Speed
2500
32nm (2013)
45nm (2010)
65nm (2007)
Achronix FPGA
(Q1 FY06)
Achronix FPGA
(Q2 FY08)
90nm
ASIC Speed
0
130nm
FPGA Speed
180nm
2000
Internal
Clock 1500
Speed
(MHz., 1000
Stated)
500
The Achronix
Differentiators:
SPEED and COST
By offering
unprecedented speed
in an economical
90nm process with
competitive power
and density
performance, we will
take the high
performance FPGA
market
13
*Source: SOCCentral.com Datasheet archive and Xilinx, Altera, Actel, Lattice Datasheets. Power not compared because reliable metrics unavailable, trends likely to mimic speed and density, 45nm and 32nm figures estimated based on trend analysis
Asynchronous dataflow computation
 Fundamentally, our FPGA operates like a traditional FPGA, but using a different model
– Asynchronous dataflow
– Tokens hold data values
– Tokens flow through pipeline stages
– Pipeline stages transform token values
 Performance
– Latency = input to output delay
– Throughput = rate at which tokens are processed
 Computation is data-driven not clock-driven
– Power savings when circuits are not doing computation
– Every gate is “clock gated”
14
Fundamentally, the components of the Achronix FPGA are identical to Altera and Xilinx
Switch Boxes (SB) routes channels between logic block
“Logic Blocks” contain the reprogrammable logic, typically in the
form of a 4-input Look Up Table (LUT) and other combinational
logic
The “Interconnect” provides the infrastructure for
communication between switch boxes on the FPGA
15
The Achronix FPGA, both at the architectural level and at the logic block level, has a very
similar design to typical Xilinx and Altera FPGAs
Altera Stratix-II Architecture and
Logic Block Diagram
Xilinx Virtex-4 Architecture and
Logic Block Diagram
Achronix Architecture and Logic
Block Diagram
High speed
synchronous I/Os
Dedicated multiplier
blocks
Embedded RAM
modules
Asynchronous high
speed
programmable logic
cells
Four-Input
LUT
State/
Conditional
Unit (Token)
Entire unit is called
“ALM – Advanced
Logic Module”
4-input LUT plus
register is called “LE
– Logic Element”
Entire unit is called
“Slice”
4-input LUT plus
register is called “LC
– Logic Cell”
4-input LUT plus Conditional unit is
called a “logic block” and is very
similar to a Xilinx “LC”
16
*Source: Altera Stratix-II datasheet, Xilinx Virtex-4LX Datasheet
The detailed circuits that comprise our logic blocks are similar to Xilinx’ “LC” Logic Cells
and Altera’s “LE” Logic Elements
Components present in Xilinx LC or Altera LE (plus clock distribution and register logic)
17
Our aggressive pipelined interconnect significant increases our performance
 Long wires through switches have poor performance
– Limits performance of traditional FPGA architectures
 ASIC solution: add repeaters/buffers
– Improves signal integrity, latency
 Aggressive solution
– Add pipeline stages to keep throughput high
– Synchronous: requires complete design re-timing because data arrives at different clock tick
 Asynchronous pipelining
– Adding pipeline stage is “almost always” safe; for deterministic computation it is always
safe
18
*Source: [MM98] R. Manohar and A.J. Martin. “Slack Elasticity in Concurrent Computing.” Proc. 4th International Conference on the Mathematics of Program Construction, Lecture Notes in Computer Science 1422, June 1998.
Our switch box architecture is nearly identical to a conventional switch box,
but when combined with our interconnect, dramatically increases our speed
Traditional Synchronous “Layered”
Interconnect
Achronix Asynchronous Pipelined
Interconnect
Traditional FPGA Deficiencies
Achronix Advantages
Increased Latency: Adding pipeline stage
encounters one cycle of latency
Reduced Latency: Adding pipeline stage
adds 0.125 cycles of latency
Interconnect Timing: Requirement of
matching numbers of flip-flops after place
and route makes pipelining impossible
Pipelined Interconnect: Token-based
model enables variations in interconnect
hop counts, minimizing latency in the
interconnect
Increased Complexity: Long-haul routes
with increased switch box complexity
fundamentally limits complexity and
density
*Source: W. Tsu et al. "HSRA: High-Speed Hierarchical Synchronous Reconfigurable Array." Proc. FPGA 1999
Modular Design: Elimination of longhaul routes and global signals enables
massive scalability
19
We tested our 180nm prototype using a variety of well known FPGA benchmarks, and
achieved unusually high throughput across a wide range of benchmarks
Achronix Measured Performance (180nm)
Altera Stratix-II Measured Performance (90nm)
Benchmarks Performance
Benchmarks Performance
700
600
500
Achronix Average
636 MHz
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Benchmarks Performance
Benchmarks Performance
100.00%
90.00%
80.00%
70.00%
Utilization of 60.00%
Maximum
50.00%
Throughput 40.00%
30.00%
20.00%
10.00%
0.00%
4 x4
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1 6-b
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Achronix Average
94.4% Utilization
8 -bi
Altera Stratix-II Average
334 MHz
um
Arr
ay M
8 -bi
4 x4
8 -bi
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1 6-b
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*Source: Altera Stratix-II “Design Building Block Performance”, August 2005, No data available for Xilinx, but performance is comparable to Altera Stratix-II
100.00%
90.00%
80.00%
70.00%
Utilization of 60.00%
Maximum
50.00%
Throughput 40.00%
30.00%
20.00%
10.00%
0.00%
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100
Altera Stratix-II Average
66.9% Utilization
um
200
Ma
xim
Throughput 400
(MHz)
300
500
450
400
350
Throughput 300
250
(MHz)
200
150
100
50
0
20
Using the same asynchronous circuit core in 90nm CMOS technology, Achronix has
designed an identical FPGA that operates at over 1GHz system throughput
180nm and 90nm Prototype Performance
90nm Simulation Data
SPICE Simulation Data
Speed - Achronix m easured in System Throughput, Others m easured in
Maxim um Internal Clock Speed
1.2
1600
1
1400
0.8
1200
0.6
Internal Clock 1000
Speed (MHz., 800
Stated)
600
Measured 674MHz
system throughput with
180nm prototype
13.78
13.44
13.61
13.1
13.27
12.76
12.42
12.93
Nanoseconds
12.59
12.08
90nm
12.25
130nm
11.74
180nm
11.91
-0.2
0
11.4
0
200
11.57
400
11.23
Achronix FPGA
0.2
10.89
11.06
ASIC Speed
0.4
10.04
10.21
10.38
10.55
10.72
FPGA Speed
FPGA Output
Simulations of 90nm prototype
range from 1.4 – 1.6GHz system
throughput
Compensated simulations predict performance in the 1.4-1.6 GHz range. We will verify the
actual system throughout when the 90nm devices return from fabrication in January 2006,
but we conservatively expect performance well over 1GHz.
21
We expect this prototype to perform at an average throughput of at least 1.3GHz (based on
simulations)
Achronix Expected Performance (90nm)
Altera Stratix-II Measured Performance (90nm)
Benchmarks Performance
Benchmarks Performance
1400
1200
1000
Achronix Average
1.32 GHz
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Benchmarks Performance
Benchmarks Performance
100.00%
90.00%
80.00%
70.00%
Utilization of 60.00%
Maximum
50.00%
Throughput 40.00%
30.00%
20.00%
10.00%
0.00%
4 x4
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Achronix Average
94.4% Utilization
*Source: Altera Stratix-II “Design Building Block Performance”, August 2005
Altera Stratix-II Average
334 MHz
um
Arr
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4 x4
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100.00%
90.00%
80.00%
70.00%
Utilization of 60.00%
Maximum
50.00%
Throughput 40.00%
30.00%
20.00%
10.00%
0.00%
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200
Altera Stratix-II Average
66.9% Utilization
um
400
Ma
xim
Throughput 800
(MHz)
600
500
450
400
350
Throughput 300
250
(MHz)
200
150
100
50
0
22
Our architecture also allows for temperature insensitivity
 Key features of class of asynchronous circuits we are using
– Tolerant to arbitrary variations in gate delay
– Tolerant to conductivity changes in wires
 CMOS devices have a wide operating range
 Nominal net effect of temperature change
– Delay change
– We have no PLLs, oscillators, or other analog circuits for clock distribution
 Asynchronous circuits are naturally temperature insensitive
– Change in temperature impacts performance, but circuits still operate correctly
23
Temperature Insensitivity
24
Temperature Insensitivity
25
Measured Peak Performance with Temperature (180nm)
AFPGA Performance
1200
1000
Frequency
800
12K
77K
294K
400K
600
400
200
0
0
0.5
1
1.5
2
2.5
Voltage
26
Radiation tolerance will be achieved by a RADHARD by design approach on SOI
 Technology + design approach
 Asynchronous self-correction for event upsets
– When a gate has an event upset (logic fault), we can wait for the upset to self-correct and
locally stall the computation
 Circuits are encoded
– Data representation used has redundancy
– Redundancy can be used for cross-checking values with a simple circuit technique
 Deep sub-micron SOI allows us to use “RADHARD by design” methods
– Gate layout geometries
 We are investigating this experimentally in 2006, but plan to support 100krad – 300krad TID
27
Agenda
Company Overview
Overview of Asynchronous Circuits
Achronix Technology & Solution Overview
Product Architecture and Specifications
28
Since our announcement about our prototype in September we have spoken to over 20
potential customers. This has driven our architecture road map.
Achronix 90nm Product Road Map
Predicted Performance – 90nm
140% increased in speed
30% reduction in power consumption
30% increase in density
50% Risk
Shipping in 1H2008
10% decrease in speed
65% reduction in power consumption
40% increase in density
25% Risk
Shipping in 2H2007
No decrease in speed
No reduction in power consumption
40% increase in density
25% Risk
Shipping in 1H2008
29
Using our familiar architecture with an asynchronous core, our first product will
significantly outperform industry leaders’ products in terms of speed and power
Power Performance (Historical Data for Asynchronous Circuits)
Device Type
Processor
16-bit Adder
Device Type
Sychronous
Orion R4600
MCC Adder
Asyhcnronous
Power Performance
Sychronous
Asyhcnronous
Metric
MIPS2/E
E/ins
MiniMIPS2V (1998)
MCC Async Adder
1125
4.7
Asychronous D
3100
3
63.71%
36.17%
Achronix expected circuit power performance: 36%-63% lower
Speed Performance
Speed - Achronix m easured in System Throughput, Others m easured in
Maxim um Internal Clock Speed
1600
Density Performance (Expected @ 90nm)
1400
1200
High Performance FPGAs
Internal Clock 1000
Speed (MHz., 800
Stated)
600
2500000
400
ASIC Speed
Achronix FPGA
2000000
200
0
180nm
130nm
90nm
ASIC Equivalent Gates
FPGA Speed
1500000
Stratix II
Virtex-4
1000000
Achronix
density band
500000
0
0.00
0.20
0.40
0.60
0.80
1.00
1.20
Cost Per Device (A.U.)
…and while our unit density is lower, our ability to scale density enables us to build
devices with comparable density as industry leaders, but at lower cost
30
*Source: Achronix testing of 180nm device, Achronix simulations of 90nm device, Pricing and density data from Xilinx and Altera Websites and AVNET list pricing from website
Since we can scale our density with die size, our supported density becomes a business
decision for our first lines of products, rather than a technical challenge
High Performance FPGAs
Target Product Specs
2500000
Achronix-ULTRA Specs
– Speed: 1.4 – 1.6 GHz throughput
ASIC Equivalent Gates
2000000
– Power: Not a pricing factor. Will be
lower than Altera Stratix-II and Xilinx
Virtex-4
1500000
Stratix II
Virtex-4
1000000
– Density: 1M to 1.5M AEG (80k-120k
LUTs)
– Op. Temp = -264 to + 130 C
500000
Achronix-XTREME Specs
– Speed: 1.0 – 1.2GHz throughput
0
0.00
0.20
0.40
0.60
0.80
Cost Per Device (A.U.)
1.00
1.20
– Power: Not a pricing factor. Will be
lower than Actel RTAX-S
– Density: 1+M AEG (80k LUTs)
– Op. Temp = -264 to + 130 C
AchronixULTRA
density-pricing
band
AchronixXTREME
density-pricing
band
– Radiation Tolerance = 100-300 krad
31
Because the Achronix FPGA is based on a familiar architecture, and utilizes synchronous
interfaces, customers can leveraging existing software infrastructure
Achronix Tool Chain
Behavioral
Verilog
C-Like Input
Easier
Verilog
Asychronous
Translator
RTL-level
Functional
Description
Bit level netlist
generator for data
flow
Place and Route
Tool
FPGA Mapped,
Placed, and
Routed
Easiest
Simulator
High-level
functional input
(MATLAB,
LABVIEW)
Easy
Achronix software development efforts will
focus on the entire tool chain, but particularly
on these component in 2006
Accepts input from any type
of description language
Example: Celoxica Interface
Example: Synplicity/Cadence/Mentor Graphics Interface
32
This aggressive hardware and software strategy will allow us to accomplish our key goals
Achronix Key Goals
Ultra fast Speed
– Support system throughputs in the 1 GHz (2006) to 2.5 GHz (2008) range through our novel asynchronous
FPGA fabric
Competitive Density and Power Performance
– While operating at GHz speeds, provide competitive density and power performance to state of the art
devices from Xilinx, Altera, Actel, and Lattice
Synchronicity and Interoperability
– At the system level, look and feel just like a traditional synchronous FPGA from Xilinx, Altera, Actel, Lattice,
and others by surrounding our fabric with traditional synchronous I/Os
Support the Existing EDA Landscape
– Support existing EDA tools used by FPGA and ASIC designers to ensure that our products can be integrated
easily and immediately and replace slower parts from or competitors
We would like to understand what other specific features/goals that the extreme
environment community would like to see in our product, and when you would like to see
the product
*Source: Simulations of Achronix 90nm design. Real results to be determined in January 2006
33
Achronix Semiconductor Corporation
427 East Seneca Street, Suite 100
Ithaca, NY, 14850
USA
Phone:
Fax:
Internet:
Email:
+1.877.GHZ.FPGA (877.449.3742)
+1.413.280.9887
http://www.achronix.com
[email protected]