Transcript Design Review Slides

Reconfigurable Systems Conceptual Design Review
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Reconfigurable Systems

Team




Client / Faculty Mentor


Dr. Joe Law
Graduate Mentor


Dr. Greg Donohoe
Lead Instructor


Chris Canine
Terseer Ityavyar
Cameron D. Dennis
John Geidl
Sponsor


NASA
UI CAMBR
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Background
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Embedded Computing

Invisible to the user
 Example:
The modern day vehicle has about 40
microprocessors

Goal: High speed with smallest footprint
 Small footprint
 Size
 Weight
 Power consumption
 Speed (computing power)

Linear system
 Computing is done
 Resources take up
logically
memory
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Reconfigurable Computing System


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Massive data path parallelism
Do many tasks at once
Flexibility is gained through reconfiguration
 Processing
Elements (PE’s)
 Interconnect
Input
PE0
IOP0
PE2
PE1
Output
FireIOP0
FirePE0
FirePE2
FirePE1
PE4
PE3
FirePE3
FirePE3
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IOP1
FireIOP1
Reconfigurable Interconnect

Current technology uses shared, parallel buses
 Limited

throughput with high power consumption
Proposed technology uses dedicated, serial data
paths with crossbar switching
 Very
high throughput
 Low power consumption
Crossbar Switching
Picture from National
Semiconductor’s “LVDS
Owner’s Manual”
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Last Year’s S.D. Project
Configurable
Memory
Module
Configurable
Memory
Module
Interconnect
Interconnect
Control
Global Clock
Processor Node
Processor Node
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Strategy
Data sink
LVDS
Data sink
serializer
Data source
Data sink
LVDS
Old approach
• LVCMOS signals
• Parallel routing
serializer
Data source
XBAR
Data sink
Data source
XBAR
LVDS
deserializer
LVCMOS
ULP 0.5V
ULP 0.5V
LVCMOS 2.5V
deserializer
Data source
LVCMOS 2.5V
New approach
• LVDS signaling
• Serial routing
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Low Voltage Differential Signaling

How it works:



Switch current direction
Input current sense
detection
Routing:



Sender
‘0’
Receiver
ZL
Dedicated forward and
return signal lines
Tailored transmission line
characteristics, field
cancellation
Minimize frequency effects,
reflection and signal
distortion
‘1’
ZL
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Low Voltage Differential Signaling
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Noise sensitivity:

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Reduced crosstalk
Robust, excellent commonmode noise rejection
Low voltage (350 mV),
higher frequencies (>1.5
GHz)
Smaller voltage swings
Power consumption:


Lower, relatively
independent of switching
frequency
To minimize power per bit,
maximize data rate through
each serial channel
2.5
0
dV 2.5V

 25 V / ns
dt 0.1ns
Standard CMOS
+0.175
-0.175
dV 0.35V

 3.5 V / ns
dt 0.1ns
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LVDS
What We Will Do
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Our Goal



To compare serial communication versus
parallel communication
Show that Low Voltage Differential Signaling
(LVDS) communication is a viable
implementation method
Highlight the benefits of LVDS including
 High-speed data transfer
 Lowered Electro-Magnetic Interference
 Low power consumption
 Reduced circuit board area
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(EMI)
Needs

A study that will
 Convince
a spacecraft system engineer to use serial
LVDS designs for reconfigurable systems
 Provide the documentation to allow the
implementation of serial LVDS designs
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Constraints
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No slower than 800 data Mbits per second
Variable path delay
Function with different delays in the
communication path
No errors detected in a bit error rate test (BERT)
in 15 minutes of continuous operation
Preferred all on one printed circuit board
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Specifications

Proof of concept
 Compare
differential, sequential communication vs.
single-ended, parallel communication.
 Power consumption – “Gigahertz @ milliWatts”

Reduced watts per bit
 Circuit
board area – Show a greatly reduced area vs.
parallel system
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Specifications (cont.)
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
Two Source Nodes
Two Destination Nodes
 Transmit
from either source to either destination
depending on a specific control signal sent to switch
the central crosspoint switch

Desirable
 Go
to two destinations from one source
 Full bidirectional communication
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Deliverables

Reports
 Compare
serial vs. parallel implementations for power
and area
 Describe a design flow using the Cadence Tools
 Proper documentation to pass on to someone else to
duplicate the design
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Deliverables (cont.)

Hardware
 Demo
a working serial system meeting the
specifications above
 Instrument as necessary to demonstrate the
specifications


Measure and report Bit Error Rate (BERT)
Measure and report power consumption
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Design Implementation Options
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Components Needed
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4 Field Programmable Gate Arrays (FPGA)
4 Serializer/Deserializer’s (SerDes)
1 Crosspoint Switch (XBAR)
LCD Displays
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Option A
DES
FPGA
DES
FPGA
assembled
 Easy setup
 LCD included
 Relative low cost
 Will reduce Speed
 Complicated pinout
SER
 Already
XBAR
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SER

FPGA
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Offboard FPGA
Onboard SerDes
Can use D2SB & DIO5
FPGA
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Option A Specifics
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Offboard FPGA
 Digilent
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D2SB/DIO5 Kit with Xilinx Spartan IIE FPGA
Onboard SerDes
 National

Onboard Crosspoint Switch
 National
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Semiconductor DS92LV18
Semiconductor SCAN90CP02
Additional Onboard Hardware
 LCD
and other display hardware is included on the
D2SB/DIO5 board
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Option B
FPGA
DES
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DES
FPGA
XBAR
SER
will allow faster
onboard communications
 Less noise / interference
 Smaller board area
 Requires more components
 Complicated layouts and chip
placements
SER
 SerDes
FPGA

Onboard FPGA’s
Onboard SerDes
FPGA

Option B Specifics

Onboard FPGA
 Xilinx

Spartan IIE FPGA
Onboard SerDes
 National

Onboard Crosspoint Switch
 National

Semiconductor DS92LV18
Semiconductor SCAN90CP02
Additional Onboard Hardware
 LCD
to display BERT results
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Option C
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XBAR
FPGA
amount of components
 More difficult VHDL
implementation
 FPGA with these abilities is
very expensive
 Less interconnect = less noise
introduction
 Smallest board size
FPGA
 Least
FPGA

Onboard FPGA’s
Use built-in SerDes capability
of FPGA’s
FPGA

Option C Specifics

Onboard FPGA
 Xilinx

Onboard SerDes
 None

Virtex Family FPGA
Required
Onboard Crosspoint Switch
 National

Semiconductor SCAN90CP02
Additional Onboard Hardware
 LCD
to display BERT results
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Our Recommendation - Option B
Reduced cost
 Ease of implementation
 All on one printed circuit board

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Projected Costs

4 x FPGA
 Xilinx

Spartan IIE FPGA - $50.00
1 x Crosspoint Switch
 National

4 x Serializer / Deserializer
 National
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

Semiconductor SCAN90CP02 - $5.00
Semiconductor DS92LV18 - $16.50
LCD and Misc. Connectors - $50.00
Printed Circuit Board Fabrication - $250.00
Total Projected Cost: $571.00
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Questions & Comments
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Work Breakdown Structure
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Option Comparison
FPGA
SerDes
XBAR
PCB
Misc
Total
Cost
D2SB/DIO5 - $0
National DS92LV18 - $16.50
National SCAN90 - $5.00
~$250
~$50
$371
Xilinx Spartan IIE - $50
National DS92LV18 - $16.50
National SCAN90 - $5.00
~$250
~$50
$571
Xilinx Virtex II - $1000
N/A - $0
National SCAN90 - $5.00
~$250
~$50
$4,305
Pros:
Easy setup, LCD
included, Relative
low cost
Option A
Cons:
May reduce speed,
complicated
connector layout
Pros:
Faster onboard
comm., Less noise,
smaller board area
Option B
Cons:
Requires more
components,
complicated pinouts
Pros:
Option C
Least amount of
components, less
interconnect,
smallest board size
Cons:
Difficult VHDL
implementation,
expensive FPGA
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