Transcript Digital System Design

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Lecture 7
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Introduction
 Comparison of Standard Logic Circuits
and Programmable Logic Circuits
 Evolution and Overview of PLC:
 PROM, PLA, PAL
 CPLD
 FPGA
Resource: Xilinx, Aleksandra Kovacevic
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Logic Circuits
Standard Logic Circuits
Programmable Logic Circuits
• Realize single function or
set of functions,
once defined
and with no possibility of
changing.
• Contains great number of
standard logic circuits
• Possibility of realizing many
various functions
• Hardware can configure
any time by user programming.
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Standard Logic Circuits
• Appropriate for many applications because of possibility
of realization in mass production for relative low cost.
• Standard logic circuits are sometimes the best choice
in high-performance devices.
• Disadvantage:
Not permitting design updates (function changes)
with no hardware replacement necessary.
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Field- Programmable Logic Devices
• Component function is defined by users program.
• Advantages:
- Ease of design changes
- Reduce prototype-product time
- Large scale integration (over 100 000 gates)
- Reliability increased, low financial risk
- Smaller device, low start-up cost
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FPLDs Representatives
Programmable
logic device
• PLA - Programmable Logic Arrays
• PAL - Programmable Array Logic
PLD
• CPLD - Complex Programmable Logic Devices
• FPGA - Field Programmable Gate Arrays
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Evolution of PLD: Why not PROM?
• A special device (called a burner),
used to put the information,
supplies an electrical current
to specific cells in the ROM that
effectively blows a fuse in them
= burning the PROM.
From that point on, chip is read-only.
• PROM was the first type of user-programmable chip;
address lines = logic circuit inputs
data lines = logic circuit outputs
• PROMs are inefficient architecture for realizing logic circuit:
Logic functions
rarely require
more than few
product terms
PROM contains
a full decoder
for its address
inputs.
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Evolution of PLD: PLA
• PLA was the first device
developed for implementing
f ( x1 ,..., xn )   ( x1 ,..., xn )
• Consist of two levels
of logic gates programmable “wired”
AND-plane & OR-plane
• Drawbacks:
• Expensive to manufacture
• Offered somewhat poor
speed-performance
Note:
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Evolution of PLD: PAL™
• Overcame weaknesses of PLA
• Single level
of programmability consists of a programmable
“wired” AND-plane & fixed ORgates
• Simpler to program
and cheaper implementation
• Limited numbers
of terms in each output
Note:
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PAL is a trademark of Advanced Micro Devices
Evolution of PLD: Register PLA
• Contain flip flops
connected to
the OR gate outputs
sequential circuits
can be realized
• Importance:
• Profound effect on
digital hardware design
• Basis for more
sophisticated architectures
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Evolution of PLD: CPLD
Programmable
possibility to produceInterconnect
devices
• Technology advanced
Array
with higher capacity than
SPLDs.
- Capable of
• Structure grows too quickly in size
connecting any
LAB input or
as the number of inputs is increased
output to any
other LAB
• Integrating multiple SPLDs onto a single chip -
the only feasible way to provide large capacity devices Logic Array
based on SPLD
Blocks
• Programmably connect the SPLD blocks together
- Complex SPLDlike structure
• Logic capacity up to the equivalent of about 50 typical SPLD devices
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... and finally...
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Evolution of PLD:
FPGA
• Difficult extending CPLDs architectures to higher
a different approach is needed
contains a set of
basic functions
(gates, FFs,- memory
densities
cells)
• FPGAs comprise an array of uncommited circuit elements,
called logic blocks, and interconnect resources
• FPGA configuration is performed through
programming by the end user.
Xilinx FPGA Configuration
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* A field-programmable gate array (FPGA) is a logic
device that contains a two-dimensional array of
generic logic cells and programmable switches.
Resource1: FPGA Prototyping By Verilog Examples,
Pong P. Chu, Wiley, 2008,
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Resource2: Xilinx DS099 Design
Specification,
* A logic cell can be configured (i.e., programmed) to
perform a simple function
* A programmable switch can be customized to provide
interconnections among the logic cells
* A custom design can be implemented by specifying the
function of each logic cell and selectively setting the
connection of each programmable switch
* Once the design and synthesis are completed, we can use a
simple adaptor cable to download the desired logic cell
and switch configuration to the FPGA device
* Since this process can be done "in the field" rather than "in
a fabrication facility (fab)," the device is known as field
programmable.
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* A logic cell usually contains a small configurable combinational circuit with a D-type
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flip-flop (DFF)
The most common method to implement a configurable combinational circuit is a
look-up table (LUT). An n-input LUT can be considered as a small 2n-by-1 memory
By properly writing the memory content, we can use a LUT to implement any n-input
combinational function
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* Most FPGA devices also embed certain macro cells or
macro blocks,
* These are designed and fabricated at the transistor
level and their functionalities complement the
general logic cells
* Commonly used macro cells include memory blocks,
combinational multipliers, clock management
circuits, and I/0 interface circuits
* Advanced FPGA devices may even contain one or more
prefabricated processor cores
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* Logic cell
* The most basic element of the Spartan-3 device is a
logic cell (LC), which contains a four-input LUT and a
DFF
* Slice
* In Xilinx terms, two logic cells are grouped to form a slice
* CLB
* Four slices are grouped to form a configurable logic block
(CLB)
* Macro Cell
* The Spartan-3 device contains four types of macro blocks:
combinational multiplier, block RAM, digital clock
manager (DCM), and input/output block (IOB)
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* Array Multiplier
* The combinational multiplier accepts two 18-bit numbers
as inputs and calculates the product
* Block RAM
* The block RAM is an 18K-bit synchronous SRAM that can be
arranged in various types of configurations
* DCM
* A DCM uses a digital-delayed loop to reduce clock skew
and to control the frequency and phase shift of a
clock signal
* IOB
* An IOB controls the flow of data between the device's I/0
pins and the internal logic. It can be configured to
support a wide variety of I/0 signaling standards.
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*Spartan-3 FPGA QFP Package for Part
Number XC3S400-4PQ208C
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1. Xilinx Spartan-3 XC3S200 FPGA device
(XC3S200FT256)
2. 2M-bit Xilinx XCF02S platform flash
configuration PROM
3. Jumper to select the configuration source
4. Two 256K-by-16 asynchronous SRAM devices
(ISSI IS61LV25616AL-10T) VGA display port
6. RS-232 serial port
7. RS-232 transceiverl voltage-level convertor
8. Second RS-232 transmit and receive channel
9. PSI2 mouse/keyboard port
10. Four-digit seven-segment LED display
11. Eight slide switches
12. Eight discrete LED outputs
13. Four momentary-contact pushbutton
switches
14. 50-MHz crystal oscillator clock source
15. Socket for an auxiliary crystal oscillator
clock source
16. Jumper to select an FPGA configuration mode
17. Pushbutton switch to force FPGA reconfiguration
18. LED to indicate whether the FPGA is successfully
configured
1 9. 40-pin expansion connector 1 (labeled B1)
20. 40-pin expansion connector 2 (labeled A2)
2 1. 40-pin expansion connector 3 (labeled A1 )
22. JTAG connector for Digilent download cable
23. Digilent low-cost download cable (included in
the S3 kit but not shown in Figure 2.3)
24. JTAG port (to be used with the Xilinx Parallel
Cable IV and MultiPRO Desktop Tool,which are not
included in the S3 kit)
25. Power connector for an unregulated 5-V power
supply (included in the S3 kit)
26. Power-on LED indicator
27. 3.3-V voltage regulator
28. 2.5-V voltage regulator
29. 1.2-V voltage regulator
30. Selector for PS2 port voltage supply (3.3 or 5 V)
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