Transcript Actuation electronics

Actuation Electronics For
(Near) Future Detectors
Alberto Gennai
[email protected]
Introduction


The VIRGO Suspensions are complex
mechanical structures used to insulate
optical elements from seismic noise. The
structure, described by an 80 vibrational
modes model, is controlled by 18 coilmagnet pairs commanded with two distinct
Digital Signal Processors operating at 10
kHz sampling frequency. The suspension
status is observed using 20 local sensors
plus optional 3 global sensors.
The new control system foresees multiDSP computing units, faster and higher
resolution analog-to-digital and digital-toanalog converters and high dynamic power
driver for coil-magnet pair actuators.
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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Last Stage Actuators

Last stage actuators
play a fundamental
role applying forces
directly on test
masses.
 This talk concentrates
on two key aspects of
actuators electronics:
– Dynamical range
– Electro-Magnetic
Immunity
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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VIRGO Suspension Control Unit





2 x Motorola PowerPC-based CPU
boards
2 x Motorola DSP96002-based boards
60 Analog I/O channels
4 Digital optical point-to-point links
(LAPP Annecy)
CCD Camera Interface (LAPP Annecy)

10 kHz Sampling
 16 (14.5 eff.) bits ADC
 20 (17.5 eff.) bits DAC
 About 100 poles for each DSP
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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Actuators Electronics Dynamical Range

Power amplifiers used to drive coilmagnet pair actuators steering VIRGO
optical elements need a wide dynamical
range:
– Big force impulse required for acquiring the
lock of VIRGO optical cavities
– Low noise during linear regime.

The rms value of correction signal
decreases while sensitivity approaches
VIRGO goal curve:
– Need of a flexible solution able to easily adapt
to sensitivity changes without limiting control
signal dynamics
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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Actuators noise: current status
-5
10

The use of a Digital to
Analog converter to
drive actuators
electronics limits the
actuator dynamic.
At present in VIRGO
we use 20 bit DAC
– Vmax = 10 V
– Vnoise = 300 nV/Hz1/2

-10
10
m/Hz 1/2

Reference Mass - Mirror Actuators Noise
Filter #7 - Marionetta Actuators Noise
VIRGO Sentivity
-15
10
-20
10
-1
10
New VIRGO coil driver
shall supply
– Imax = 2 A
– Inoise = 3 pA/Hz1/2
0
1
10
10
Frequency (Hz)
Coil Driver
2
3
10
10
Ref. Mass Coil
DAC
RCoil
10
+
OUT
1
-
LCoil
3mH
R2
R
R1
R
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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6
New Coil Drivers

A new coil driver was designed using
two distinct sections:
– high power section for lock acquisition
– low noise section for linear regime.

The two sections are driven by two
independent digital-to-analog converter
channels.
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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New Coil Driver: Basic Operation

Dynamical range extension is
obtained using two DAC
channels.
1. DAC #1 is used during
lock acquisition phase (2A
current). During this
phase DAC #2 is set to
zero.
2. DAC #1 is then set to zero
and simultaneously DAC
#2 is activated
3. High power section is
disconnected from coil
actuator
Cascina, June 9th 2005
Transconductance Amplifier
DAC 1
Coil Driver
Ref. Mass Coil
DAC 2
A.Gennai (INFN Pisa)
+
RCo i l
10
RN
O UT
5 00
-
1
L Co i l
3 mH
R2
R
R1
R
2
8
DAC Noise Contribution
-12
10
-13
10
VIRGO Goal Sensitivity
Coil Driver with 26 kOhm series resistor
Coil Driver with 4 kOhm resistor + De-Emphasis filter
-14
10
-15
PSD (m/sqrt(Hz))
10
-16
10
-17
10
-18
10
-19
10
-20
10
Simulated data
-21
10
0
10
1
2
10
10
3
10
Frequency (Hz)
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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New Coil Driver: Block Diagram



For each actuator three distinct section are available (one
High Power plus two Low Noise).
The High Power section is a transconductive amplifier able
to supply up to 2 A into the coil while the two Low Noise
sections are voltage amplifiers with series resistor
The three sections architecture will allow switching from
lock acquisition to linear lock regime in two (or more) steps.
Analog IN #1
High Power
Section
Coil
Analog IN #2
Low Noise
Section #1
Low Noise
Coil Current
Monitor
Low Noise
Section #2
Serial Link
Control
Section
High Power
Coil Current
Monitor
Analog OUT #1
Analog OUT #2
• Sections switch
• Gain selection
• De-enphasis filtering
• Monitor configuration
10
Prototype (installed at terminal towers)
8
Coil Up
Coil Down
Switch
Time
6
Current Monitor
4
2
0
-2
-4
-6
-8
0
10
20
30
Time (s ec)
40
50
60
10
20
30
Time (sec)
40
50
60
-4
2.04
x 10
2.03
2.02
Transmitted Power
2.01
2
1.99
1.98
1.97
1.96
1.95
1.94
0
Experimental Results
10
0
High Power GPS 778606100
Low Noise GPS 778606730
High Power GPS 778606970
Low Noise GPS 778607600
10
PSD (V/sqrt(Hz))
10
10
10
-1
Bad EMI due to bad PCB
-2
-3
-4
200 A/V
DAC noise floor
10
-5
Current monitoring noise
10
-6
10
0
Cascina, June 9th 2005
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1
2
10
Frequency (Hz)
10
3
A.Gennai (INFN Pisa)
DAC noise floor with new coil driver
10
4
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Electro-Magnetic Immunity

Power Supply
– Only linear power supply is allowed. Supply
shall be separated from analog circuits. A star
grounding scheme shall be adopted.

PCB
– Multi-layer circuit boards with signal lines
sandwiched between ground planes.
–…

Circuits Shielding
– Analog and digital circuits shall be separated
with independent Faraday shielding.
– Shielded crates shall be utilized

External Wiring
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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EMI – External Wiring



Each coil driver is connected
via a 30 meters long
Shielded Twisted Pair (STP)
cable to the digital to analog
converter (DAC) board.
To improve EMI/EMC, digital
to analog and analog to
digital converters, shall be
made available on-board.
Processing nodes shall be
connected to front end
electronics using
galvanically isolated wiring
with optical or RF couplers
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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Coil Drivers: Digital I/O
DAC
Digital IN
Digital
IF
DAC
10 Mb/sec digital
data electrically
isolated
High Power
Section
Coil
High Power
Coil Current
Monitor
Low Noise
Section #1
Digital OUT
Low Noise
Coil Current
Monitor
Low Noise
Section #2
Serial Link
Cascina, June 9th 2005
Control
Section
ADC
ADC
• Sections switch
• Gain selection
• De-enphasis filtering
• Monitor configuration
A.Gennai (INFN Pisa)
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Digital I/O

Several devices shall be connected to the
same serial line therefore selected
communication protocol shall support
multipoint (multiplex) transmission mode
where multiple transmitters and receivers
share the same line.
 A single fiber optic link shall provide the
connectivity between front end electronics
and processing nodes.
 IEEE 1394b-2002 standard will be adopted for
physical layer
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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Facing “Control Noise”

In addition to standard noise sources, a
new contribution, referred as “Control
Noise”, is becoming more and more
relevant
 Control noise is the noise injected into the
system by non optimal design of control
algorithms often due to limited online
computing resources
 To face this problem we decided to
drastically increase the computation
power of processing units
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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Multiprocessor DSP Board: Main Features


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6 x 100 MHz ADSP211160N SHARC DSP
3.4 GigaFLOPS
1800 MB/s of low latency inter processor
communication bandwidth
 512 MB SDRAM
 64-bit 66 MHz PCI bus
 On board 32-bit Master-Slave PCI to DSP Local
Bus bridge
 256 kWord real Dual Port memory (PCI – DSP LB)
 VME to PCI Master – Slave bridge
 DSP LB to VSB bridge for I/O devices access
 200 MB/s auxiliary I/O bandwidth
 2 x Altera EP1C4 Cyclone FPGA
 Compact size: PMC standard (149 x 74 mm)
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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Dual Port
Memory
MDSPAS – Top View
4
3
2
5
6
1
DSP
Cascina, June 9th 2005
M
A
B
FPGA
A.Gennai (INFN Pisa)
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MDSPAS – Bottom View
PCI 64 – 66 MHz
SDRAM
I/O  TimDOL
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
VSBbus20
How use 3.2 GFLOPS?

Digital Feedback Design in VIRGO
– Usual specifications:
“Use high loop gain over some frequency range
then decrease the gain as rapidly as possible”
– Classical Design Methods (SISO)
• Discrete-time controllers derived from
continuous-time controllers (indirect design
techniques)
– Design a continuous-time controller and then
obtain the corresponding discrete-time controller
using a transformation from G(s) to G(z).
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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Feedback Design Methods

Classical Design Methods (SISO)
– Root locus method
– Nyquist techniques (design based on frequency response)
– PID Controller design methods
• Transient response method
• Stability limit method

State Space Design Methods (SISO – MIMO)
–
–
–
–

Pole Placement
Optimal Control - LQG Methods
H-Infinity
...
Adaptive Control
– Model Reference adaptive control
– Self-tuning regulators
– …
Cascina, June 9th 2005
Additional computational
power will allow implementing
MIMO and adaptive
controllers, with major
advantages from the so called
“control noise” point of view
A.Gennai (INFN Pisa)
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Conclusions

Improving VIRGO sensitivity at low
frequency requires huge dynamical range
actuators electronics
 Dynamical range can be improved using
different hardware configurations for lock
acquisition and linear lock phases
 A good “stand-alone” device can easily
become a bad one once installed. Special
care shall be devoted to devices
interconnections and EMI
 Use of “clever” control algorithm
Cascina, June 9th 2005
A.Gennai (INFN Pisa)
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