Transcript VIRGO Electronics & Software Commissioning

The New Low Noise Control System
For The VIRGO Suspensions
Alberto Gennai
The VIRGO Collaboration
Digital Feedback Design in VIRGO

Classical Design Methods
– Discrete-time controllers derived from
continuous-time controllers (indirect design
techniques)
• Design a continuous-time controller and then obtain
the corresponding discrete-time controller using a
bilinear transformation from G(s) to G(z).
– SISO Systems (when MIMO, systems are
diagonalized)
• Nyquist techniques (design based on frequency
response)
Australia-Italy Workshop
October 4-7 2005
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VIRGO Suspension Control Unit
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2 x Motorola PowerPC-based CPU
boards
2 x Motorola DSP96002-based boards
60 Analog I/O channels
4 Digital optical point-to-point links
CCD Camera Interface
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10 kHz Sampling
16 (14.5 eff.) bits ADC
20 (17.5 eff.) bits DAC
About 90 poles for each DSP
Floating Point Single Extended
Precision (40 bits)
Biquad sections are implemented
using first order filters with complex
coefficients, this allowing a better
precision on poles/zeros locations
and much better performances from
the numerical round-off noise.
VIRGO DSP Application Process View
WS
rioA
DSP
User
User Interface
Cm
EServerDSP
VME
DSP OS
Trigger
DSP ISR
Analog
I/O
DAQ
Global
Control
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Timing And Time Delay (I)
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Basic timing sequence: time delay  TS
Sampling Period
ADC
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Processing
DAC
ADC
Processing
DAC
VIRGO DSP timing sequence: time delay  2 TS
Sampling Period
ADC
ADC
Processing
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October 4-7 2005
DAC
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Processing
DAC
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Timing And Time Delay (II)
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Total Delay Contributions
– Sampling Period
• ADC and DAC conversion time
• Processing Time
• ISR latency and context switch time
– DAC Hold Time = 0.5 TS
– Anti-Aliasing and Reconstruction Filters
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Total Delay (Local Control)
T = 2 Ts + 0.5 TS + 4 TS = 6.5 Ts
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(TS = 100 sec)
For Global Control we need one additional
TS for GC processing
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October 4-7 2005
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VIRGO DSP
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About 80 usecs available for computation
8 poles + 8 zeros = 1 usec
Current limits
– Total number of variables + total number of filters
coefficients cannot exceed 512 (128 var + 384 coeff). In
terms of number of singularities we have a maximum of
128 poles + 128 zeros that can be extended up to 192
poles and 192 zeros allowing some additional
computation time.
• This limit was reached and big efforts are now needed in
code optimization
– Computation Time: close to limit for DSP controlling
suspension top stage.
– I/O: Limited number of I/O channels (40)
• Limit reached and influencing some architectural choice.
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DSP processor obsolete
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October 4-7 2005
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DSP Code Example: MC Local Control
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On top of already
quite complex
algorithms, new
functionalities
were added:
– Mirror position
memory
– Automatic re-lock
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October 4-7 2005
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contBS
contPR
contNI
contWI
contWE
contNE
contMC
contIB
contOB
dampPR
dampBS
dampWE
dampNE
dampNI
dampIB
dampOB
dampMC
dampWI
contABP
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DSP Usage (08-2005)
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New Control System
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Scope
– Upgrade of the main control loops of Virgo
(suspensions, injection, locking and alignment) aiming
to faster and higher dynamical range control systems.
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Motivations
– The control system currently in use is operative since
1998 (project started in 1994) and it is now approaching
its limits in terms of performances for available
computational power, converters dynamical range and
components availability.
– The new control system foresees multi-DSP computing
units, faster and higher resolution analog-to-digital and
digital-to-analog converters and high dynamic power
driver for coil-magnet pair actuators.
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Running activities and development plan
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New Signal Processing Board
– Design completed in October 2004
– First prototype currently under test (September 2005)
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New Coil-Driver
– Prototypes currently installed at VIRGO terminal towers
and beam splitter tower.
– Final design completed January 2005
– First production and installation in 2006
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New Digital to Analog Converter Board
– Early design phase
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Software Development
– Preliminary design phase for both DSP compiler and top
level control software
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Multiprocessor DSP Board: Main Features
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6 x 100 MHz ADSP211160N SHARC DSP
3.4 GigaFLOPS in single PMC Mezzanine
1800 MB/s of low latency inter processor communication bandwidth
512 MB SDRAM, 4 MB ZBT SRAM, 4Mbit FLASH EPROM
64-bit 66 MHz PCI bus ready
Up to 2 x PC/104-Plus Intel Celeron 933 MHz modules with Fast Ethernet
interface running Linux OS
1 PMC Mezzanine site for optional PowerPC or Pentium based CPU
1 PMC Mezzanine site for digital optical link and timing interface
On board 32-bit Master-Slave PCI to DSP Local Bus bridge
256 kWord real Dual Port memory (PCI – DSP LB)
VME to PCI Master – Slave bridge
DSP LB to VSB bridge for I/O devices access
200 MB/s auxiliary I/O bandwidth
IEEE 1149.1 JTAG Standard Test Access Port
2 x Altera EP1C4 Cyclone FPGA
Advanced software support from Altera Quartus II suite
VisualDSP++ support
Virgo DSP compiler
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Why 3 GFLOPS ?
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Additional computational power will allow
implementing MIMO and adaptive
controllers, with major advantages from the
so called “control noise” point of view
 Present DSPs are overloaded by data
reduction and processing activities that
cannot be handled by the central VIRGO
data acquisition system. Multiple DSPs will
allow keeping on implementing such
functionalities without loading nodes
devote to control tasks.
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DSP Functional Blocks Diagram
VME
PCI2VME
Bridge
Fast
Ethernet
PCI2PCI
Bridge
PC104Plus
CPU Module
Console
PCI
Link Port
4
DOL
ZBT
Cyclone
EP1C4
Dual Port
Memory
2
DSP
#5
DSP
#3
2
DSP
#1
Serial link
DSP Local Bus
SDRAM
Cyclone
EP1C4
Flash
Memory
Timing
4
DSP
#6
DSP
#4
Link Port
2
Serial link
DSP
#2
2
Link Port
3
Front Panel
VSB
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DSP Board Description
ADSP 21160N DSP
Like other SHARCs, the ADSP-21160N is a 32-bit processor that is optimized
for high performance DSP applications.
The ADSP-21160N features include an 95 MHz core, a 4M-bit dual-ported onchip SRAM, an integrated I/O processor that supports 14 DMA channels,
multiple internal buses to eliminate I/O bottlenecks, two serial ports, six link
ports, external parallel bus, and glueless multiprocessing.
The ADSP-21160N introduces Single-Instruction, Multiple-Data (SIMD)
processing. Using two computational units (ADSP-2106x SHARC DSPs have
one), the ADSP-21160N can double performance versus the ADSP-2106x on a
range of DSP algorithms.
With its SIMD computational hardware running at 95 MHz, the ADSP-21160N
can perform 570 million math operations per second.
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Dual Port
Memory
MDSPAS – Top View
4
3
2
5
6
1
DSP
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M
A
B
FPGA
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MDSPAS – Bottom View
PCI 64 – 66 MHz
SDRAM
I/O

TimDOL
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VSBbus17
MDSPAS Layout Summary
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Layout Statistics:
Components: 404
Nets: 838
Pins: 5103
Equivalent ICs (1 pin = 1/14 EIC): 364
Layout area (sq in): 17.0
Layout density (sq in/EIC): 0.047
Pin density (Pins/sq in): 300.280
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Connection Statistics:
Connections: 4005
Manh Distance (inches): 2707.9
Etch Length (inches): 3836.51
Number of Vias: 7193
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DSP Board: First prototype under test
MDSPAS – Lay up and vias
Nr Name
1 TOP
2 L2
3 GNDT
4 L4
5 VDDI
6 VCORE
7 L7
8 VDDE
9 L9
10 GNDB
11 L11
12 BOTTOM
Type
CONDUCTOR
DIELECTRIC
CONDUCTOR
DIELECTRIC
PLANE
DIELECTRIC
CONDUCTOR
DIELECTRIC
PLANE
DIELECTRIC
PLANE
DIELECTRIC
CONDUCTOR
DIELECTRIC
PLANE
DIELECTRIC
CONDUCTOR
DIELECTRIC
PLANE
DIELECTRIC
CONDUCTOR
DIELECTRIC
CONDUCTOR
Material
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
FR-4
COPPER
Thickness (um)
35
150
35
150
35
150
35
150
35
150
35
150
35
150
35
150
35
150
35
150
35
150
35
Via Pad Size (um)
400
Drill Size (um)
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October 4-7 2005
VIA2T VIA4T VIA6T VIA6B VIA4B VIA2B VIAP VIAPP
710
450
400
400
400
200
400
400
450
710
400
400
450
710
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400
450
710
400
450
710
400
450
710
400
450
710
400
450
710
200
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710
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450
710
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400
400
450
710
400
200
400
200
400
200
450
250
710
400
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Motherboard Top
DOL
& Timing
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VME
Connectors
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(INFN Pisa)
DSP
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Motherboard Bottom
PC104Plus
9.5 x 9
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PC104Plus
9.5 x 9
VME
Connectors
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(INFN Pisa)
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New Coil Drivers
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Power amplifiers used to drive coil-magnet pair actuators
steering VIRGO optical elements need a dynamical range
wider than what initially foreseen due to the big force
impulse required to acquire the lock of VIRGO optical
cavities.
A new coil driver was designed using two distinct sections:
one high power section for lock acquisition and one low
noise section for linear regime. The two sections are driven
by two independent digital to analog converter channels.
The new coil driver can supply up to 3 A during the lock
acquisition phase with a few nA/Hz1/2 of noise during linear
regime.
A final version of the new coil driver will host three distinct
sections and the possibility to add digital to analog
converters on board to improve EMI/EMC
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Overview and Motivations
Actuators
current
status
Initialnoise:
VIRGO
setup
-5
10
Actuator noise:
current
status
Reference
Mass - Mirror
Actuators Noise
Filter #7 - Marionetta Actuators Noise
VIRGO Sentivity
-10
m/Hz 1/2
10
-15
10
-20
10
-1
10
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October 4-7 2005
0
10
1
10
Frequency
(Hz)
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(INFN
Pisa)
2
10
3
10
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New Coil Driver: Basic Operation
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Dynamical range extension is obtained using two DAC channels.
– DAC #1 is used during lock acquisition phase (3A current). During
this phase DAC #2 is set to zero.
– DAC #1 is then set to zero and simultaneously DAC #2 is activated
– Finally, high power section is disconnected from coil actuator
– DAC #2 noise contribution is reduced by series resistor
(500 pA/sqrt(Hz) current noise flowing in the coil)
Transconductance Amplifier
DAC 1
De -emphasys Filter
1
C1
1
2
Re lay
2
R2
R
DAC 2
Coil Driver
R1
R
OUT
+
RCoil
10
RN
+
OUT
500
-
1
LCo il
3mH
R2
R
R1
R
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2
Re f. Mass Coi l
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Preliminary Desing (Protoype)
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October 4-7 2005
A prototype was developed modifying
existing coil drivers to test theory of
operation
Control functionalities were
implemented using external devices
A.Gennai (INFN Pisa)
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Preliminary Desing (cont.)
No problems were noticed
during prototype operation
(now installed at terminal
and beam spltter mirrors)
excluding ...
10
8
Coil Up
Coil Down
Switch
Time
6
Current Monitor
4
2
0
-2
0
-4
High Power GPS 778606100
Low Noise GPS 778606730
High Power GPS 778606970
Low Noise GPS 778607600
-6
10
10
PSD (V/sqrt(Hz))
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10
10
-1
-8
0
10
20
30
Time (s ec)
40
50
60
-2
-3
-4
200 A/V
DAC noise floor
10
-5
Current monitoring noise
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October 4-7 2005
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-6
10
0
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10
3
DAC noise floor with new coil driver
27 10
4
Preliminary Desing (cont.)
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...EMC problems (not deeply investigated up today)
Sc__NE__RM__CoilD
High Power GPS 778606100
Low Noise GPS 778606730
High Power GPS 778606970
Low Noise GPS 778607600
-3
PSD (V/sqrt(Hz))
10
-4
10
-5
10
100
200
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October 4-7 2005
300
400
500
600
Frequency (Hz)
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700
800
900
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Expected performances
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de-emphasis filter with p = 2  rad/sec and z = 60  rad/sec
-12
10
-13
10
VIRGO Goal Sensitivity
Coil Driver with 26 kOhm series resistor
Coil Driver with 4 kOhm resistor + De-Emphasis filter
-14
10
-15
PSD (m/sqrt(Hz))
10
-16
10
-17
10
-18
10
-19
10
-20
10
-21
10
0
10
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Workshop
October 4-7 2005
1
2
10
10
Frequency
(Hz) Pisa)
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(INFN
3
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New Coil Driver: Block Diagram
Analog IN #1
High Power
Section
Coil
Analog IN #2
Low Noise
Section #1
Low Noise
Coil Current
Monitor
Low Noise
Section #2
Serial Link
Control
Section
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October 4-7 2005
High Power
Coil Current
Monitor
Analog OUT #1
Analog OUT #2
• Sections switch
• Gain selection
• De-enphasis filtering
• Monitor configuration
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Coil Drivers: Improved EMI
24bits
DAC
Digital IN
Digital
IF
10 Mb/sec digital
data electrically
isolated
24bits
DAC
High Power
Section
Coil
High Power
Coil Current
Monitor
Low Noise
Section #1
Digital OUT
Low Noise
Coil Current
Monitor
Low Noise
Section #2
Serial Link
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October 4-7 2005
Control
Section
24bits
ADC
24bits
ADC
• Sections switch
• Gain selection
• De-enphasis filtering
• Monitor configuration
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Coil Drivers: Preliminary Layout
Eurocard Module (3U)
Control
DAC / ADC (optional)
Analog Sections
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October 4-7 2005
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32
New Digital to Analog Converter Board

The need of a very high dynamical range
for actuators has an impact also on digital
to analog converter boards. The board
currently in use has -98 dB of total
harmonic distortion + noise while newer
chips are available on market with –120 dB
thus allowing a factor 10 gain in the DAC
dynamical range.
 Two different architectures:
– Standard VME board, 16 ch. 24bits (nominal)
– Distributed system
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October 4-7 2005
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New Analog to Digital Converter Board
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Operation up to 100 kSamples/sec at very
high resolution (24 bits nominal , 20 bit
equivalent) (LAPP Annecy)
– As for Digital-to-analog converters we are
investigating the possibility to distribute
converters to front-end electronics to improve
EMI.
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2 MSamples/sec at lower resolution (16
bits nominal, 14 bit equivalent).
– The goal is being able to replace any analog
control loop with a digital one:
• Laser frequency stabilization.
• Laser power stabilization.
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October 4-7 2005
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34
Conclusions

The new VIRGO control system, based on multiDSP computing units, will allow operation up to
100 kSamples/sec at very high resolution (16
effective bits ADC, 20 effective bits DAC) and up
to 2 MSamples/sec at lower resolution (14
effective bits ADC, 16-18 effective bits DAC) thus
allowing extending applications range.
 A first prototype of new multi-DSP board is
currently under test in our lab.
 Installation plan is quite complex.
– Late 2006
• New DSP installation
• New DAC and coil drivers electronics for payloads controls
– 2007
• New ADC boards
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October 4-7 2005
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