Transcript Noise Tolerant VLSI - Rice University Electrical and Computer

Low-power Multimedia Wireless
Communication Systems
Naresh R. Shanbhag
Coordinated Science Laboratory
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
URL://uivlsi.csl.uiuc.edu/~vips/
1
Trends and Problems in
Integrated Circuits
(Source: Semiconductor Industry Association 1997 Roadmap)
Current day Integrated Circuit
0.2 micron
3.7M/sq.cm
750 MHz
250 MHz
1.8-2.5V
70 Watts
1.2 Watts
0.5-0.75 micron
Integrated Circuit in 2012*
0.035 micron
DENSITY
180M/sq.cm
ON-CHIP CLOCK
10 GHz
OFF-CHIP CLOCK
1.54 GHz
SUPPLY VOLTAGE
0.5-0.6V
POWER (HIGH PERF.)
175 Watts
POWER (MOBILE)
3.2 Watts
WIRE PITCH
0.1-0.15 micron
FEATURE SIZE
• Problems (due to Systems-on-a-chip in deep submicron)
– Time-to-market/Design productivity vs. Design complexity => Solutions:
Design reuse via Intellectual Property; Design exploration; H/S codesign,
Reconfiguration
– Reliability: noise, signal integrity, process variations => Solutions: noise
analysis, smart place&route, noise-tolerance
– Design efficiency: low-power and high-speed techniques & bounds
2
Integrated Multimedia
Communication Systems
(Source: www.ti.com/sc/docs/wireless/97/issues.htm)
Source
(video/
speech/
data)
Source
Proc./
Coding
Channel
Coding
Modulation
RF
Channel
• Additional Problems:
– mixed-signal issues: coupling, low-voltage analog, etc.
• Additional Solutions: DSP and communication theory; joint sourcechannel coding, signal-adapted DSP, multiresolution DSP; welldefined system/algorithm design
3
Multimedia
Communication System
Design
Standards
(VDSL, ATM
Wireless, Video)
Specifications
System Design
IC Design
IC Fab&Test
• Projects:
– Wireline system design: ATM-LAN, VDSL, cable modem (Goel, Hegde,
Tschanz)
– Wireless system design: (Wang)
– Hermitian decoder ASIC (Profs. Blahut and Kotter, Ashbrook, Feng)
– Low-power transforms and synthesis: (Profs. Hajj and Najm, Ramprasad,
Hegde)
4
Noise-tolerant VLSI
Architecture
Algorithmic Noise-Tolerance
Architectural Noise-Tolerance
Logic
Logic Noise-Tolerance
Circuit
Noise-Tolerant Circuits
Noise Propagation
Algorithm
Noise Models
Noise Analysis/Measurements
• Projects:
– Algorithmic noise-tolerance (Hegde, Wang)
– Noise-tolerant circuits (Wang, Ganesh)
– Noise-tolerant distributed arithmetic filters (Anders)
5
Deep Submicron (DSM)
Noise
Noise Sources:
•
Ground bounce
•
IR drop
•
Crosstalk
•
Charge sharing
•
Charge leakage
•
Process variations
•
Alpha particles
•
Electro-magnetic
radiation
VDD
M1
NIC-GB
D
F
F
Q
VSS
Q
Error
D
(b)
Noise Problems: aggressive architectural (deep pipelining) and circuit
(dynamic, low-voltage) styles.
6
Mirror Technique For
Dynamic Circuit
F
F
Vout
Vin1
NMOS
LOGIC
VinN
Vin1
F
(a) Conventional domino
F
Vout
Vin1 Vin2
NMOS
LOGIC
VinN
Vout
NMOS
LOGIC
F
(b) Mirror technique
F
(c) NAND gate design
7
ANTE:
A Noise-Tolerance Metric
• Average Noise Threshold Energy
Cnic1


2
ANTE  E Vnoise
Tnoise
Cnic2
• Energy Normalized ANTE
NANTE 
Error Free
ANTE

 : Energy dissipated per cycle
Noise Immunity Curve
8
Simulation Results:
Full Adder
Mirror technique
Static
Conventional dynamic
Design Specifications:
(1) Power supply: 3.3V
(2) Load capacitor: 20fF
(3) Clock cycle: 1GHz
Technology: 0.35 micron CMOS
Area Energy
(m 2 ) (pJ )
Static
574.3 2.202
Conventional dynamic 288.8 0.889
Mirror tech.
487.2 1.693
ANTE
( nJ )
3.115
1.405
5.203
Energy
Normalized ANTE
1414
1580
3073
9
Noise-Tolerant ASIC
Technology: 0.35m CMOS
Pin #: 48
Transistor #: ~ 20K
Area: ~ 5mm2
Technique: dynamic, mirror noise-tolerant dynamic
Measured Noise immunity improvement: 34.1% ~ 69.5%, average:
55.2%
10
Soft DSP
FROM A/D
TO A/D
LATCH
DSP BLOCK
LATCH
DELAY
CLOCK-PERIOD
CLOCK
Vdd-crit
SUPPLY VOLTAGE
TRADITIONAL DSP DESIGN
• critical-path-delay of the DSP block < sample period.
• reduction in supply voltage to the DSP block is limited by Vdd-crit.
Soft DSP
• reduce Vdd beyond Vdd-crit.
• detect/correct errors in output via Algorithmic Noise-Tolerance.
MEET THE SNR/BER CRITERION AT REDUCED ENERGY DISSIPATION.
11
Error Probability in
Arithmetic Units
PATH-DELAY DISTRIBUTION OF 8-BIT RIPPLE CARRY ADDER
1
factor by which energy dissipation
reduces
x100% input combinations
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
delay in multiples of FA delay
8
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
probability of error
• 48% reduction in energy dissipation possible with prob. of err. = 0.1
• distribution with long tail leads to smaller error penalty
• errors at the AU level lead to SNR/BER degradation
• Algorithmic Noise-Tolerance to enhance performance
12
Algorithmic NoiseTolerance (ANT)
^
y(n)
y(n) yerr (n)
x(n)
SOFT DSP
Error
Control
IDEAL :
e(n)
e(n)  0 when y err (n)  0
e(n)  0 when y err (n)  0
ANT via LINEAR PREDICTION:
• exploit the correlation in filter output to perform error-control
• optimum predictor for error detection - minimize MSE e(n)
^
y(n)
x(n)
SOFT DSP
FILTER
ep (n)  e(n)  yerr (n)
D
e p (n)
D
D
h1
hN-1
hN
0
ep (n) when yerr(n) = 0
ep (n)+ yerr (n)
13
Frequency Selective
Filtering via Soft DSP
difference-based
ANT-based
70
SNR desired = 20dB
% reduction in energy dissipation
65
60
55
50
45
40
35
0
5
• difference-based scheme :
10
15
20
25
SNR at the filter output
• 52% power savings with 1dB SNR loss (effective for high correlation).
• prediction-based scheme:
• 44% power savings with 0.7dB SNR loss (overhead: 2-tap predictor)
• effective for low correlation (higher BW).
14
Information-Theoretic
VLSI Framework
Algorithm:input
stats.,I/O map
R
Implementation
arch., circuit, tech.,
DSM noise
C
Achievable bounds
on reliability and
efficiency
• Information Transfer Rate:
R (bits/sec)
• Information Transfer Capacity:
C (bits/sec)
• For reliability : C > R; For energy-efficiency: C  R
• Projects:
Soft DSP
– Lower-bounds on energy-efficiency of noisy digital circuits (Hegde)
– Lower-bounds on signal transition activity and coding schemes
(Ramprasad, Prof. Hajj)
– Bounds on: throughput and energy-efficiency; adaptive systems (Goel)
– Design techniques for ultra efficient VLSI
15
Lower Bound on Energy
Dissipation
Information Transfer Rate : R
Transition Activity : t
N
CL
Operating Speed : f c
• Minimize:
Eb = (Pdyn+ Pstat)/R bits/sec
subject to:
C  R
• operating point:
fc = kmVdd/ CL



Q(Vdd/2 
N. R. Shanbhag, University of Illinois at Urbana-Champaign
16
Dynamic Power
Energy dissipation at minimum supply voltage
is greater than minimum achievable energy
dissipation
N. R. Shanbhag, University of Illinois at Urbana-Champaign
17
Reconfigurable DSP
Input
Signal Processing
Algorithm
(SPA)
Control
Signals
Auxiliary
Signals
Signal Monitoring
Algorithm
(SMA)
• Dynamic Algorithm Transforms:
Output
Reconfigurable
data-path
(ASIC, FPGA,
multi-processor)
Controller
(ROM,microprocessor,
ASIC)
min Energy/Throughput
subject to: DSP constraint
• Projects:
–
–
–
–
–
Low-power adaptive filtering, VDSL equalizer ASIC (Goel, Tschanz)
Domain-specific reconfigurable DSP processors (Tschanz)
Reconfigurable DSP for video processing (Minocha)
FPGA board design (Park)
Video over wireless (Profs. Jones and Ramchandran)
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Dynamic Algorithm
Transforms (DAT)
A framework for designing low-power
reconfigurable DSP systems
Input statespace S
DSP
models
Configuration
space C
min Energy
s.t. J < Jo
Energy
models
Energy-optimum
configuration
19
Input State-space S
• Set of all possible input states
Received signal power
1000
pt(s1,s2)
Good channel G
100
10
pt(s1,s1)
s1=G
1
s2=B
pt(s2,s2
)
pt(s2,s1)
Bad channel B
0.1
p(s1)
0.01
0
0.1
0.2
time
Signal power received at the mobile unit
mobile speed = 60 miles/hr
RF signal frequency = 2 GHz
0.3
p(s2)
• s(n) = received signal power
• Two-state model
• State s1 : Good channel
• State s2 : Bad channel
• p(si) : steady-state probabilities
• pt(si,sj) : transition probabilities
20
Configuration-space C
• Set of all possible configuration vectors
the reconfigurable datapath can support
x(n)
x(n-1)
D
D
x(n-N+1)
0
0
0
w1
w2
wN
a
a2
D
aN
y(n)
Nth TAP
c(n)=[a,a2,….,aN] : N-bit configuration vector
C: Set of all N-bit tuples (2N vectors)
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Very High-speed Digital
Subscriber Loop
FIBER
TWISTED PAIR DISTRIBUTION CABLE
ONU
• Cable length
– 100ft to 1kft (worstcase)
• Far-end crosstalk
System Data-rate
Distance
ADSL
1.544 Mb/s 18 kft
ADSL
8.448 Mb/s 9 kft
VDSL
12.96 Mb/s 4.5 kft
VDSL
51.84 Mb/s 1 kft
– 4-11 interferers
• Desired BER=10-7
– SNR=21.5dB
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51.84 Mb/s VDSL
Transmitter
In-phase shaping filter
51.84
Mb/s
Scrambler
16-CAP
Encoder
DAC
LPF
Q-phase shaping filter
51.84 MHz
Imag
Real
– square-root raised cosine
Analog Front End
– excess bandwidth=36%
– center frequency=12.96 MHz
16-CAP signal constellation
23
DAT-based 51.84 Mb/s
VDSL Receiver
PGA
Control
I-PHASE
EQUALIZER
a,b
A/D
Timing
Recovery
SLICER
W,e(n)
FBF
SMA BLOCK
a,b
PGA
+
Q-PHASE
EQUALIZER
W,e(n)
SLICER
+
D
E
C
O
D
E
R
DSCRAMB
51.84 Mb/s
– I/Q-phase equalizers: 48 taps each
– FBF: 10 complex strength-reduced taps
– Powers of two LMS + Blind Equalization
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80
60
20
40
60
40
20
0
0
0
0.2
0.4
0.6
0.8
1
2
4
6
8
10
12
-20
-20
Energy Savings (%)
80
Energy Savings (%)
100
100
Energy Savings:
51.84 Mb/s VDSL
Cable length (kft)
VARIATIONS IN CABLE LENGTH
Number of FEXT interferers
VARIATIONS IN FEXT INTERFERERS
AVERAGE ENERGY SAVINGS=53%
25
Wireless Environment
MULTIPATH CHANNEL
ANTENNA
BASE
STATION
ANTENNA
MULTI-USER
INTERFERENCE
MOBILE
Flexibility Features of IMT-2000 systems
• Adaptability
of system to time-varying propagation and traffic environments
• Adaptation to different spectrum allocations
• Ability to accommodate mixed-cell (pico, micro and macro) architecture
• Ability to handle different services: audio, video, speech,data, multimedia
26
Reconfigurable Wireless
Communication System
• With Doug Jones and Kannan Ramchandran
Distortion and BER
SNR
Wireless
Image
Video
Source
Encoder
Rs
Channel
Encoder
t
Power
Amplifier
Pt
Source
Decoder
Rs
Channel
Decoder
t
RAKE
Receiver
crake
OUTER TRANSCEIVER
Wireline
INNER
TRANSCEIVER
c opt (si )  arg min Energy (c)
• Energy-optimum configuration
via Dynamic Algorithm Transforms
D(c, si )  Do
and Joint Source-Channel Coding s.t. 
27
 R tot (c)  R o
carphone
100
akiyo
t=32
0
coastguard
t=24
0.5
Probability of error
t=16
1
Average Distortion per pixel
10000
1
Source-Channel
Variabilities
0
1
2
Source Rate (in bits per pixel)
(Rate-Distortion Curves)
SOURCE VARIABILITIES
3
4.5
5.5
6.5
7.5
Channel SNR (Eb/No)
(BER Curves)
CHANNEL VARIABILITIES
28
akiyo
carphone
akiyo
carphone
claire
coastguard
claire
coastguard
container
hall_objects
container
hall_objects
mother_and_daughter
silent
mother_and_daughter
silent
0.002
0.002
0.0016
0.0016
Energy (in J/pixel)
Energy (in J/pixel)
Simulation Results: QCIF
Images and IMT-2000
Test channels
0.0012
0.0008
0.0004
0
0.0012
0.0008
0.0004
0
0
20
40
60
80
distance (in m)
Channel A (low delay spread)
100
0
20
40
60
80
100
distance (in m)
Channel B (medium delay spread)
• Energy Savings: maximum 93% (average 59%)
• Fraction of Energy due to the digital blocks:
– ranges from 40-10% (for distance: 10-100m)
29
Summary
• Evolving next generation (3G) wireless standards: flexibility and
energy-efficiency.
• Evolving integrated circuit technology: deep submicron noise, complex
system-on-a-chip (SOC).
• DSP via Soft Computations (Soft DSP): energy-efficient,
noise-tolerant circuit design and algorithmic noise-tolerance
• Dynamic low-power techniques are required
– inter-application dynamism => domain-specific processors
– intra-application dynamism => run-time reconfiguration
• Dynamic algorithm transforms: input space, configuration space,
DSP models, energy models, joint-optimization of energy
& performance
30