Transcript VLSI Design Lecture 3a: Nonideal Transistors

VLSI Design
Lecture 3a:
Nonideal Transistors
Outline
 Transistor I-V Review
 Nonideal Transistor Behavior
 Velocity Saturation
 Channel Length Modulation
 Body Effect
 Leakage
 Temperature Sensitivity
 Process and Environmental Variations
 Process Corners
Ideal Transistor I-V
 Shockley 1st order transistor models


0

 
V
I ds    Vgs  Vt  ds
2


2


Vgs  Vt 


2
Vgs  Vt
V V  V
 ds
ds
dsat

cutoff
linear
Vds  Vdsat saturatio n
Ideal nMOS I-V Plot
 180 nm TSMC process
 Ideal Models



 = 155(W/L) A/V2
Vt = 0.4 V
VDD = 1.8 V
Ids (A)
400
Vgs = 1.8
300
Vgs = 1.5
200
Vgs = 1.2
100
0
Vgs = 0.9
Vgs = 0.6
0
0.3
0.6
0.9
1.2
1.5
1.8
Vds
Simulated nMOS I-V Plot
 180 nm TSMC process
 BSIM 3v3 SPICE models
 What differs?
Ids (A)
250
V gs = 1.8
200
V gs = 1.5
150
V gs = 1.2
100
V gs = 0.9
50
V gs = 0.6
0
0
0.3
0.6
0.9
Vds
1.2
1.5
Simulated nMOS I-V Plot
 180 nm TSMC process
 BSIM 3v3 SPICE models
I (A)
ds
 What differs?



Less ON current
No square law
Current increases
in saturation
250
V gs = 1.8
200
V gs = 1.5
150
V gs = 1.2
100
V gs = 0.9
50
V gs = 0.6
0
0
0.3
0.6
0.9
Vds
1.2
1.5
Velocity Saturation
 We assumed carrier velocity is proportional to E-field

v = Elat = Vds/L
 At high fields, this ceases to be true


Carriers scatter off atoms
Velocity reaches vsat




sat
Electrons: 6-10 x 106 cm/s
Holes: 4-8 x 106 cm/s
Better model
μElat
v
 v sat  μE sat
Elat
1
Esat
sat / 2
slope = 
0
0
E sat
2Esat
Elat
3Esat
Vel Sat I-V Effects
 Ideal transistor ON current increases with VDD2
2
W Vgs  Vt 

I ds  Cox
 V gs V t 
L
2
2
2
 Velocity-saturated ON current increases with VDD
I
C
W
V
v
V
d
s
o
x
g
s
t
m
a
x
 Real transistors are partially velocity saturated



Approximate with -power law model
Ids  VDD
1 <  < 2 determined empirically
-Power Model

0
Vgs  Vt
cutoff

V

I ds   I dsat ds V ds  V dsat
linear
Vdsat


Vds  Vdsat saturation
 I dsat
Ids (A)
I dsat  Pc
300
Vgs = 1.8
200
Vgs = 1.5
100
Vgs = 1.2
0
Vgs = 0.9
Vgs = 0.6
0
0.3
0.6
0.9
2
V gs  V t 
Vdsat  Pv Vgs  Vt 
Simulated
-law
Shockley
400

1.2
1.5
1.8 V
ds

 /2
Channel Length Modulation
 Reverse-biased p-n junctions form a depletion
region



Region between n and p with no carriers
Width of depletion Ld region grows with reverse bias
Leff = L – Ld
 Shorter Leff gives more current
 Ids increases with Vds
 Even in saturation
GND
Source
VDD
Gate
VDD
Drain
Depletion Region
Width: Ld
n+
L
Leff
n+
p
bulk Si
GND
Chan Length Mod I-V
Ids (A)
400
I ds 

V

2
 Vt  1  Vds 
Vgs = 1.8
300
2
gs
Vgs = 1.5
200
Vgs = 1.2
100
0
0
Vgs = 0.9
Vgs = 0.6
0.3
0.6
0.9
1.2
1.5
  = channel length modulation coefficient
 not feature size
 Empirically fit to I-V characteristics
1.8 Vds
Body Effect
 Vt: gate voltage necessary to invert channel
 Increases if source voltage increases
because source is connected to the channel
 Increase in Vt with Vs is called the body effect
Body Effect Model


V
V

V


t
t
0 
s
s
b
s
 s = surface potential at threshold
s  2vT ln


NA
ni
Depends on doping level NA
And intrinsic carrier concentration ni
  = body effect coefficient
 
t ox
 ox
2q si N A 
2q si N A
Cox
OFF Transistor Behavior
 What about current in cutoff?
 Simulated results
 What differs?

Current doesn’t go
to 0 in cutoff
I ds
1 mA
Saturation
Region
Subthreshold
Region
100 A
10 A
Vds = 1.8
1 A
100 nA
10 nA
Subthreshold
Slope
1 nA
100 pA
10 pA
Vt
0
0.3
0.6
0.9
V gs
1.2
1.5
1.8
Leakage Sources
 Subthreshold conduction

Transistors can’t abruptly turn ON or OFF
 Junction leakage

Reverse-biased PN junction diode current
 Gate leakage

Tunneling through ultrathin gate dielectric
 Subthreshold leakage is the biggest source in
modern transistors
Subthreshold Leakage
 Subthreshold leakage exponential with Vgs
V gs Vt
I ds  I ds0e
nvT
Vds

 1  e vT






Ids0 vT2e1.8
 n is process dependent, typically 1.4-1.5
DIBL
 Drain-Induced Barrier Lowering

Drain voltage also affect Vt
Vt Vt Vds
VVV
ttds

High drain voltage causes subthreshold
leakage to ________.
DIBL
 Drain-Induced Barrier Lowering

Drain voltage also affect Vt
Vt Vt Vds
VVV
ttds

High drain voltage causes subthreshold
leakage to increase.
Junction Leakage
 Reverse-biased p-n junctions have some
leakage
 VvDT

I D  I S  e  1




 Is depends on doping levels


p+
And area and perimeter of diffusion regions
Typically < 1 fA/m2
n+
n+
p+
p+
n well
p substrate
n+
Gate Leakage
 Carriers may tunnel thorough very thin gate oxides
 Predicted tunneling current (from [Song01])
10 9
tox
VDD trend
0.6 nm
0.8 nm
2
JG (A/cm )
10 6
10 3
1.0 nm
1.2 nm
10 0
1.5 nm
1.9 nm
10 -3
10 -6
10 -9
 Negligible for older processes
0
 May soon be critically important
0.3
0.6
0.9
VDD
1.2
1.5
1.8
Temperature Sensitivity
 Increasing temperature


Reduces mobility
Reduces Vt
 ION ___________ with temperature
 IOFF ___________ with temperature
Temperature Sensitivity
 Increasing temperature


Reduces mobility
Reduces Vt
 ION decreases with temperature
 IOFF increases with temperature
I ds
increasing
temperature
Vgs
So What?
 So what if transistors are not ideal?

They still behave like switches.
 But these effects matter for…





Supply voltage choice
Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation
Parameter Variation
fast
 Transistors have uncertainty in parameters
 Process: Leff, Vt, tox of nMOS and pMOS
 Vary around typical (T) values
pMOS
 Fast (F)
 Leff: ______
 Vt: ______
 tox: ______
 Slow (S): opposite
 Not all parameters are independent
for nMOS and pMOS
FF
SF
TT
FS
slow
SS
slow
nMOS
fast
Parameter Variation
 Transistors have uncertainty in parameters



Leff: short
Vt: low
tox: thin
 Slow (S): opposite
fast
 Fast (F)
FF
SF
pMOS

Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values
TT
FS
SS
slow

slow
 Not all parameters are independent
for nMOS and pMOS
nMOS
fast
Environmental Variation
 VDD and T also vary in time and space
 Fast:


VDD: ____
T: ____
Corner
Voltage
Temperature
1.8
70 C
F
T
S
Environmental Variation
 VDD and T also vary in time and space
 Fast:


VDD: high
T: low
Corner
Voltage
Temperature
F
1.98
0C
T
1.8
70 C
S
1.62
125 C
Process Corners
 Process corners describe worst case
variations

If a design works in all corners, it will probably
work for any variation.
 Describe corner with four letters (T, F, S)
 nMOS speed
 pMOS speed
 Voltage
 Temperature
Important Corners
 Some critical simulation corners include
Purpose
Cycle time
Power
Subthrehold
leakage
Pseudo-nMOS
nMOS
pMOS
VDD
Temp
Important Corners
 Some critical simulation corners include
Purpose
nMOS
pMOS
VDD
Temp
Cycle time
S
S
S
S
Power
F
F
F
F
Subthrehold
leakage
F
F
F
S
Pseudo-nMOS S
F
?
?