Transcript v GS
Lecture 28 Field-Effect Transistors ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. NMOS Transistor ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. NMOS Transistor ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation in the Cutoff Region iD 0 for vGS Vto ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation Slightly Above Cut-Off By applying a positive bias between the Gate (G) and the body (B), electrons are attracted to the gate to form a conducting n-type channel between the source and drain. The positive charge on the gate and the negative charge in the channel form a capacitor where: A WL C gate d t ox ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation Slightly Above Cut-Off The amount of negative charge that accumulates in the channel is given by: Q C gate (vGS Vto ) This amount of charge is able to move a distance L from the source to the drain in a time given by: L L L2 velocity E v DS ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation Slightly Above Cut-Off The initial current flow for low drain-source voltage is given by: i DS charge in transit Q transit time C gate (vGS Vto ) L2 v DS W Lt ox (vGS Vto )v DS ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation Slightly Above Cut-Off iDS W Lt ox (vGS Vto )v DS For small values of vDS, iD is proportional to vDS. The device behaves as a resistance whose value depends on vGS. ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation in the Triode Region iD C 2 2 vGS vto vDS vDS W KP C L 2 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation in the Saturation Region iD C vGS Vto 2 vGD Vto at the transition into saturation vGD vGS v DS vGS v DS Vto at the boundary vGS v DS Vto 2 iD Cv DS ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.1 Consider an NMOS transistor having Vto=2V. What is the region of operation (triode, saturation, or cutoff) if: 1. vGS = 1V and vDS = 5V? Cutoff since vGS <Vto 2. vGS = 3V and vDS = 0.5V? Triode since vGS >Vto and vDS<vGS - Vto 3. vGS = 3V and vDS = 6V? Saturation since vGS >Vto and vDS>vGS – Vto 4. vGS = 5V and vDS = 6V? Saturation since vGS >Vto and vDS>vGS - Vto ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.2 Suppose that we have an NMOS transistor with KP = 50A/V2, Vto = 1V, L = 2m and W = 80m. Sketch the drain characteristics for vDS from 0 to 10V and vGS=0, 1, 2, 3 and 4V. For vGS= 0 or 1V, the transistor is cutoff and the drain current is zero. In the saturation region: C KP W 1 6 80 2 (50 x10 ) 1ma / V 2 L 2 2 I D C (vGS Vto ) 2 The boundary between the triode and saturation regions occurs when vDS vGS Vto vGS (V ) iD (mA) v DS 2 I D CvDS 2 3 4 1 4 9 1 2 3 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.2 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. PMOS Transistor p+ p+ n ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. MOSFET Summary ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.3 Suppose that we have an PMOS transistor with KP = 25A/V2, Vto = -1V, L = 2m and W = 200m. Sketch the drain characteristics for vDS from 0 to -10V and vGS= 0, -1, -2, -3 and -4V. For vGS= 0 or -1V, the transistor is cutoff and the drain current is zero. In the saturation region: C KP W 1 6 200 2 (25 x10 ) 1.25 ma / V 2 L 2 2 I D C (vGS Vto ) 2 The boundary between the triode and saturation regions occurs when vDS vGS Vto vGS (V ) iD (mA) v DS 2 I D CvDS 2 3 4 1.25 5 11 .25 1 2 3 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.3 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit v DD RD iD t vDS t ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit To establish the load line, we first locate two points on it: v DD RD i D t v DS t For vDD = 20V and RD=1k 20V 1ki D t v DS t i D 0 v DS 20V v DS 20V 0 iD 20 mA 1k ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit The quiescent operating point (Q point) is found for vin = 0V vGS (t ) vin (t ) 4V 4V for vin 0V ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit The maximum gate-to-source voltage is found for vin = 1V vGS (t ) vin (t ) 4V 5V for vin 1V ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit The minimum gate-to-source voltage is found for vin = -1V vGS (t ) vin (t ) 4V 3V for vin 1V ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Peak to peak swing of vGS is 2V Peak to peak swing of vDS is 12V 12 " AV " 6 2 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. The output is not proportional to the input. The output goes down by 7V for a change of +1V on the input. The output goes up by 5V for a change of -1V on the input. The output is said to be “distorted”. This is due to the uneven spacing of the characteristic curves. +5V vDSQ=11V -7V ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit Uneven spacing of the drain characteristics ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.4 Find vDSQ, vDSmin and vDSmax if the circuit values are changed to VDD=15V, VGG=3V: 15V 3V vGS (t ) vin (t ) 3V 3V for vin 0V 2V for vin -1V 4V for vin 1V ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.4 To establish the load line, we first locate two points on it: v DD RD i D t v DS t For vDD = 15V and RD=1k 15V 1ki D t v DS t i D 0 v DS 15V v DS 15V 0 iD 15 mA 1k ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.4 vGSQ 3V for vin 0V vGSmin 2V for vin -1V vGSmax 4V for vin 1V vDSQ=11V vDSmin=6V vDSmax=14V ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. FET Logic ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. CMOS Inverter ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Two-Input CMOS NAND Gate ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Two-Input CMOS NOR Gate ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.