Transcript Fault Tolerant LEON-3

An Implementation Study on Fault Tolerant
LEON-3 Processor System
Z. Stamenković
IHP
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany
www.ihp-microelectronics.com
© 2006 - All rights reserved
Outline
•
Radiation and fault tolerance
•
System description
•
Implementation details
•
Test results
•
Under way
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Slide 2
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Reliability Issues in Radiation Environments
•
Single-event upset (SEU)
A change of state caused by a charged particle strike to a
sensitive volume in a microelectronic device
Alpha particles (helium-4 nuclei) emitted by radioactive atoms found
in packaging materials
Thermal neutrons in certain device materials that are heavily doped
with 10B
High-energy terrestrial cosmic rays (play a major role)
•
SEU-induced latch-up
A failure mechanism of CMOS integrated circuits characterized
by excessive current due to parasitic PNPN paths
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Fault Tolerance of LEON-3 Processor
•
SEU tolerance by design (Gaisler Research)
Triple-module-redundancy (TMR) on all flip-flops
Three copies of a flip-flop
Two of three voting on output
Register file error-correction (up to 4 errors per 32-bit word)
Cache RAM error-correction (up to 4 errors per tag or 32-bit word)
Autonomous and software transparent error handling
No timing impact due to error detection or correction
Fault-tolerant memory controller
Provides an Error Detection And Correction Unit (EDAC)
Corrects one and detects two errors
•
Not immune to SEU-induced latch-up (in present IHP technology)
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LEON-3 Processor System
Scan-I/F
FT Add-on
EJTAG
LEON_3FT
Core
Bridge
2 kByte
I- Cache
AHB
8 Reg. Windows
2 kByte
D- Cache
FT Memory
Controller
UART 0
Serial 0
UART 1
Serial 1
APB
8 x GPIO
Scan Test
GPIO
1 x 24bit
Timer
FT Add-on
EDAC
SRAM
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FLASH
Slide 5
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Implementation Details
•
Installation of the release
•
Adaptation of the configuration tool (to include IHP’s library)
•
Implementation of data and instruction caches
•
Logic synthesis of the design
•
Implementation of scan chain
•
Generation of the chip layout
•
Simulation (functional, post-synthesis and post-layout net-list)
•
Scan test vectors generation (ATPG)
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Scan test simulation
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Adaptation of testbenches
•
EVCD test vectors generation
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Test specification
•
Documentation
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Slide 6
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Chip Features
LEON-3
Area (mm2)
22
Number of signal ports
105
Number of power ports
20
Number of scan ports
Transistors (x106)
Cache Memory (kB)
Scanable Flip-Flops (x103)
Power/Frequency (mW/MHz)
Max Frequency (MHz)
Cache
Array
I/D Data
I/D Tag
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Size
(KB)
2.5
0.5
No. of
Words
512
128
Data
Width
36 of 40
29 of 32
1 (3)
0.83
6
15
6.2
160
Address
Width
9
7
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Test System (Gaisler Research)
•
Target hardware consists of a small mezzanine with Fault Tolerant
LEON-3 device mounted on a development board (Pender Electronic
Design)
•
Board communicates with a host system (a laptop PC) over one of
the on-chip UARTs
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Test Execution (Gaisler Research)
•
Heavy-ion-error injection
Chamber with the vacuum of
10-2 mbar
Californium (Cf-252) source
Flux of 25 particles/s/cm2 at the
device surface for 3 hours
•
“Paranoia” program makes a
large number of calculations and
registers any computational error
or anomaly
•
On-chip monitoring logic
reported 281 effective SEU errors,
of which 99% were corrected
•
Cross-section for a memory RAM
bit was measured to 7.2x10-8 cm2
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Under Way
Protection against SEU-induced latch-up
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Slide 10
© 2006 - All rights reserved