Transcript LEON-2 for Wireless Engine

LEON-2: General Purpose Processor
for a Wireless Engine
Z. Stamenković
IHP
Im Technologiepark 25
15236 Frankfurt (Oder)
Germany
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany
www.ihp-microelectronics.com
© 2006 - All rights reserved
Concept
Application
Location Aware
Service Platform
•
To realize a vertical strategy from
application to silicon
picoJava
Application
Java VM
Presentation
Session
Transport (TCP)
Network (IP)
Data Link Control
Physical
IHP Innovations for High Performance Microelectronics
Slide 2
Management:
• Power
consumption
• Performance
© 2006 - All rights reserved
Wireless Engine
•
Vertical approach from application to silicon can significantly
improve the inter-layer performance characteristics
•
Wireless engine is a system-on-chip solution for mobile
computing terminals based on the vertical approach
Protocol
Protocol
Engine
Engine
DLC
DLC
IHP Innovations for High Performance Microelectronics
Application
Application
Engine
Engine
Power
Power
Management
Management
Baseband
Baseband
Slide 3
Test
Test
Engine
Engine
RF
RF
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Wireless Engine Projects
•
Wireless Broadband Network (WBN)
Single chip communication system for wireless data
transfer in the 5GHz band with a rate of about 6 to 54 Mbit/s
•
Wireless Internet (WI)
Vertical protocol optimization: power efficiency,
performance
•
TCP
IP
DLC
Mobile Computing (MoCo)
Service platform:
Location aware
Java based
IHP Innovations for High Performance Microelectronics
App
PHY
Slide 4
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LEON-2 Processor System
I-Cache
DSU
CPU
DCL
AHB
Irq Ctrl
AHB Controller
IO Port
D-Cache
Memory
Controller
UARTs
SRAM
IHP Innovations for High Performance Microelectronics
AHB/APBBridg
e
APB
Timers
Flash
Slide 5
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Implementation of LEON-2 Processor System
•
Installation of the release
•
Adaptation of the configuration tool (to include IHP’s library)
•
Implementation of data and instruction caches
•
Implementation of BIST logic for SRAMs
•
Logic synthesis of the design
•
Implementation of scan chain
•
Generation of the chip layout
•
Simulation (functional, post-synthesis and post-layout net-list)
•
Scan test vectors generation (ATPG)
•
BIST and scan test simulation
•
Adaptation of testbenches (SPARC CC installed)
•
EVCD test vectors generation (with and without timing data)
•
Test specification
•
Documentation
IHP Innovations for High Performance Microelectronics
Slide 6
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Chip Features
LEON-2
Area (mm2)
Number of signal ports
111
Number of power ports
16
Number of BIST ports
16
Number of scan ports
Transistors (x106)
1 (3)
1.5
Cache Memory (kB)
Scanable Flip-Flops (x103)
20
11.2
Power/Frequency (mW/MHz)
Max Frequency (MHz)
8.9
83
Cache
Array
I/D Data
I/D Tag
IHP Innovations for High Performance Microelectronics
Slide 7
27
Size
(KB)
8
2
No. of
Words
2048
512
Data
Width
32
23 of 32
Address
Width
11
9
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