Transcript CSE 477. VLSI Systems Design

CSE477
VLSI Digital Circuits
Fall 2002
Lecture 06: Static CMOS Logic
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg477
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
CSE477 L06 Static CMOS Logic.1
Irwin&Vijay, PSU, 2002
Review: CMOS Process at a Glance
Define active areas
Etch and fill trenches

One full photolithography
sequence per layer
(mask)

Built (roughly) from the
bottom up
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
4
2
3
1
metal
polysilicon
exception!
source and drain diffusions
tubs (aka wells, active areas)
Create contact and via windows
Deposit and pattern metal layers
CSE477 L06 Static CMOS Logic.2
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CMOS Circuit Styles

Static complementary CMOS - except during switching,
output connected to either VDD or GND via a lowresistance path

high noise margins
- full rail to rail swing
- VOH and VOL are at VDD and GND, respectively





low output impedance, high input impedance
no steady state path between VDD and GND (no static power
consumption)
delay a function of load capacitance and transistor resistance
comparable rise and fall times (under the appropriate transistor
sizing conditions)
Dynamic CMOS - relies on temporary storage of signal
values on the capacitance of high-impedance circuit
nodes


simpler, faster gates
increased sensitivity to noise
CSE477 L06 Static CMOS Logic.3
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Static Complementary CMOS

Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
In1
In2
PUN
InN
In1
In2
InN
pull-up: make a connection from VDD to F
when F(In1,In2,…InN) = 1
F(In1,In2,…InN)
PDN
pull-down: make a connection from F to
GND when F(In1,In2,…InN) = 0
NMOS transistors only
PUN and PDN are dual logic networks
CSE477 L06 Static CMOS Logic.4
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Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0  VDD
VGS
S
CL
VDD  0
PDN
D
VDD
S
CSE477 L06 Static CMOS Logic.6
CL
0  VDD - VTn
CL
VGS
VDD  |VTp|
S
CL
D
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Construction of PDN
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NMOS devices in series implement a NAND function
A•B
A
B

NMOS devices in parallel implement a NOR function
A+B
A
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B
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Dual PUN and PDN

PUN and PDN are dual networks


DeMorgan’s theorems
A+B=A•B
[!(A + B) = !A • !B or !(A | B) = !A & !B]
A•B=A+B
[!(A • B) = !A + !B or !(A & B) = !A | !B]
a parallel connection of transistors in the PUN corresponds to a
series connection of the PDN

Complementary gate is naturally inverting (NAND,
NOR, AOI, OAI)

Number of transistors for an N-input logic gate is 2N
CSE477 L06 Static CMOS Logic.8
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CMOS NAND
A
A
B
F
0
0
1
0
1
1
1
0
1
1
1
0
B
A•B
A
B
A
B
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CMOS NOR
B
A
A+B
A
A
B
F
0
0
1
0
1
0
1
0
0
1
1
0
B
A
B
CSE477 L06 Static CMOS Logic.10
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Complex CMOS Gate
B
A
C
D
OUT = !(D + A • (B + C))
A
D
B
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C
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Standard Cell Layout Methodology
Routing
channel
VDD
signals
GND
What logic function is this?
CSE477 L06 Static CMOS Logic.13
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OAI21 Logic Graph
X
A
j
C
C
B
X = !(C • (A + B))
C
i
A
i
X
B
VDD
j
B
A
B
C
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PUN
GND
A
PDN
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Two Stick Layouts of !(C • (A + B))
A
C
B
A
B
C
VDD
VDD
X
X
GND
GND
uninterrupted diffusion strip
CSE477 L06 Static CMOS Logic.15
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Consistent Euler Path

An uninterrupted diffusion strip is possible only if there
exists a Euler path in the logic graph

Euler path: a path through all nodes in the graph such that
each edge is visited once and only once.
X
C
i
X
B
VDD
j
GND

A
A B C
For a single poly strip for every input signal, the Euler
paths in the PUN and PDN must be consistent (the same)
CSE477 L06 Static CMOS Logic.17
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OAI22 Logic Graph
A
C
B
D
X
D
X = !((A+B)•(C+D))
C
D
A
B
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C
VDD
X
B
A
B
C
D
PUN
A
GND
PDN
Irwin&Vijay, PSU, 2002
OAI22 Layout
A
B
D
C
VDD
X
GND

Some functions have no consistent Euler path like
x = !(a + bc + de) (but x = !(bc + a + de) does!)
CSE477 L06 Static CMOS Logic.19
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XNOR/XOR Implementation
XNOR
XOR
A
A
AB
B
A
B
B
AB
A
B
AB

How many transistors in each?

Can you create the stick transistor
layout for the lower left circuit?
CSE477 L06 Static CMOS Logic.20
AB
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VTC is Data-Dependent
0.5/0.25 NMOS
0.75 /0.25 PMOS
3
A
M3 B
M4
2
A,B: 0 -> 1
B=1, A:0 -> 1
A=1, B:0->1
F= A • B
D
A
1
M2
VGS2 = VA –VDS1
S
D
B
M1
VGS1 = VB
S
weaker
PUN
Cint
0
0

1
2
The threshold voltage of M2 is higher than M1 due to the
body effect ()
VTn1 = VTn0
VTn2 = VTn0 + ((|2F| + Vint) - |2F|)
since VSB of M2 is not zero (when VB = 0) due to the presence of Cint
CSE477 L06 Static CMOS Logic.21
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Static CMOS Full Adder Circuit
!Cout = !Cin & (!A | !B) | (!A & !B)
!Sum = Cout & (!A | !B | !Cin) | (!A & !B & !Cin)
B
A
B
B
A
Cin
A
B
Cin
Cin
!Cout
!Sum
A
A
B
B
A
Cin
A
B
Cin
A
B
Cout = Cin & (A | B) | (A & B)
CSE477 L06 Static CMOS Logic.23
Sum = !Cout & (A | B | Cin) | (A & B & Cin)
Irwin&Vijay, PSU, 2002
Next Time: Pass Transistor Circuits
A
AB
B
CSE477 L06 Static CMOS Logic.24
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Next Lecture and Reminders
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Next lecture

Pass transistor logic
- Reading assignment – Rabaey, et al, 6.2.3
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Reminders
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Project Title due today !
Lecture 5 will be next Thursday (guest lecturer)
HW2 due September 24th
Evening midterm exam scheduled
- Wednesday, October 10th from 8:15 to 10:15pm in 260 Willard
- Only one midterm conflict filed for so far
CSE477 L06 Static CMOS Logic.25
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