Transcript CSE 477. VLSI Systems Design - University of California

CSE477
VLSI Digital Circuits
Fall 2002
Lecture 07: Pass Transistor Logic
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg477
[Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]
CSE477 L07 Pass Transistor Logic.1
Irwin&Vijay, PSU, 2002
Review: Static Complementary CMOS

High noise margins

VDD
In1
In2
In1
In2
InN

Low output impedance, high
input impedance

No static power consumption
PUN
InN
F(In1,In2,…InN)
PDN
PUN and PDN are dual logic networks
CSE477 L07 Pass Transistor Logic.2
VOH and VOL are at VDD and
GND, respectively

Never a direct path between
VDD and GND in steady state

Delay a function of load
capacitance and transistor on
resistance

Comparable rise and fall
times (under the appropriate
relative transistor sizing
conditions)
Irwin&Vijay, PSU, 2002
Review: Static CMOS Full Adder Circuit
!Cout = !Cin (!A v !B) v !A !B
!Sum = Cout (!A v !B v !Cin) v !A !B !Cin
B
A
B
B
A
Cin
A
B
Cin
Cin
!Cout
!Sum
A
A
B
B
A
Cin
A
B
Cin
A
B
Cout = Cin (A v B) v A B
CSE477 L07 Pass Transistor Logic.3
Sum = !Cout (A v B v Cin) v A B Cin
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NMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain
terminals

NMOS switch closes when the gate input is high
A
B
X
Y
X = Y if A and B
A
X

B
X = Y if A or B
Y
Remember - NMOS transistors pass a strong 0 but a
weak 1
CSE477 L07 Pass Transistor Logic.4
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PMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain
terminals

PMOS switch closes when the gate input is low
A
B
X
Y
X = Y if A and B = A + B
A
X

B
X = Y if A or B = A  B
Y
Remember - PMOS transistors pass a strong 1 but a
weak 0
CSE477 L07 Pass Transistor Logic.5
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Pass Transistor (PT) Logic
B
B
A
0
B
F =AB
A
B
F =AB
0
Gate is static – a low-impedance path exists to both
supply rails under all circumstances
 N transistors instead of 2N
 No static power consumption

Ratioless
 Bidirectional (versus undirectional)

CSE477 L07 Pass Transistor Logic.7
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VTC of PT AND Gate
B
1.5/0.25
2
A
Vout, V
0.5/0.25
B=VDD, A=0VDD
1
0.5/0.25
B
0
0.5/0.25

A=VDD, B=0VDD
A=B=0VDD
F= AB
0
0
1
2
Pure PT logic is not regenerative - the signal
gradually degrades after passing through a number
of PTs (can fix with static CMOS inverter insertion)
CSE477 L07 Pass Transistor Logic.8
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Differential PT Logic (CPL)
B
A
A
B
B
PT Network
A
A
B
B
Inverse PT
Network
B
B
F
F=AB
B
B
F=AB
B
AND/NAND
CSE477 L07 Pass Transistor Logic.9
B
A
F=A+B
B
A
A
F
B
A
A
F
F
A
F=AB
A
F=A+B
B
F=AB
A
OR/NOR
XOR/XNOR
Irwin&Vijay, PSU, 2002
CPL Properties

Differential so complementary data inputs and outputs
are always available (so don’t need extra inverters)

Still static, since the output defining nodes are always
tied to VDD or GND through a low resistance path

Design is modular; all gates use the same topology, only
the inputs are permuted.

Simple XOR makes it attractive for structures like adders

Fast (assuming number of transistors in series is small)

Additional routing overhead for complementary signals

Still have static power dissipation problems
CSE477 L07 Pass Transistor Logic.10
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CPL Full Adder
B
Cin
B
Cin
A
!Sum
A
Sum
B
B
Cin
A
B
!Cout
Cin
A
B
CSE477 L07 Pass Transistor Logic.12
Cin
Cout
Cin
Irwin&Vijay, PSU, 2002
NMOS Only PT Driving an Inverter
In = VDD
A = VDD
VGS
D
Vx =
VDD-VTn
M2
S
B
M1

Vx does not pull up to VDD, but VDD – VTn

Threshold voltage drop causes static power
consumption (M2 may be weakly conducting forming a
path from VDD to GND)

Notice VTn increases of pass transistor due to body
effect (VSB)
CSE477 L07 Pass Transistor Logic.13
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Voltage Swing of PT Driving an Inverter
3
In
In = 0  VDD
1.5/0.25
x
Out
0.5/0.25
B
0.5/0.25
Voltage, V
S
VDD
D
2
x = 1.8V
1
Out
0
0
0.5
1
1.5
2
Time, ns

Body effect – large VSB at x - when pulling high (B is
tied to GND and S charged up close to VDD)

So the voltage drop is even worse
Vx = VDD - (VTn0 + ((|2f| + Vx) - |2f|))
CSE477 L07 Pass Transistor Logic.14
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Cascaded NMOS Only PTs
B = VDD
B = VDD C = VDD
G
A = VDD
M1
S
C = VDD
x = VDD - VTn1

M1
x
M2
y
Out
G
y
M2
Out
S
Swing on y = VDD - VTn1 - VTn2

A = VDD
Swing on y = VDD - VTn1
Pass transistor gates should never be cascaded as on
the left
Logic on the right suffers from static power dissipation
and reduced noise margins
CSE477 L07 Pass Transistor Logic.15
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Solution 1: Level Restorer
Level Restorer
on
Mr
off
B
A=1
A=0
Mn
x= 0
1
M2
Out=0
Out =1
M1

Full swing on x (due to Level Restorer) so no static
power consumption by inverter

No static backward current path through Level Restorer
and PT since Restorer is only active when A is high

For correct operation Mr must be sized correctly (ratioed)
CSE477 L07 Pass Transistor Logic.16
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Transient Level Restorer Circuit Response
3
W/L2=1.50/0.25
W/Ln=0.50/0.25
W/L1=0.50/0.25
Voltage, V
2
W/Lr=1.75/0.25
node x never goes below VM
of inverter so output never
switches
W/Lr=1.50/0.25
1
W/Lr=1.25/0.25
W/Lr=1.0/0.25
0
0

100
200
Time, ps
300
400
500
Restorer has speed and power impacts: increases the
capacitance at x, slowing down the gate; increases tr (but
decreases tf)
CSE477 L07 Pass Transistor Logic.17
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Solution 2: Multiple VT Transistors

Technology solution: Use (near) zero VT devices for the
NMOS PTs to eliminate most of the threshold drop (body
effect still in force preventing full swing to VDD)
low VT transistors
In2 = 0V
A = 2.5V
on
Out
off but
leaking
In1 = 2.5V
B = 0V
sneak path

Impacts static power consumption due to subthreshold
currents flowing through the PTs (even if VGS is below VT)
CSE477 L07 Pass Transistor Logic.18
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Solution 3: Transmission Gates (TGs)

Most widely used
solution
C
C
A
A
B
B
C
C
C = GND
A = VDD
B
C = VDD

C = GND
A = GND
B
C = VDD
Full swing bidirectional switch controlled by the gate
signal C, A = B if C = 1
CSE477 L07 Pass Transistor Logic.20
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Resistance of TG
W/Lp=0.50/0.25
30
0V
25
Rn
Rp
Resistance, k
20
2.5V
Vout
Rp
Rn
15
2.5V
10
Req
W/Ln=0.50/0.25
5
0
0
CSE477 L07 Pass Transistor Logic.21
1
2
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TG Multiplexer
S
S
S
S
F
S
VDD
In2
S
F
In1
S
F = !(In1  S + In2  S)
GND
In1
CSE477 L07 Pass Transistor Logic.22
In2
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Transmission Gate XOR
weak 0 if !A
off
on
A
off
on
0
B
1
CSE477 L07 Pass Transistor Logic.24
A  !B
AB
B  !A
weak 1 if A
an inverter
Irwin&Vijay, PSU, 2002
TG Full Adder
Cin
B
A
Sum
Cout
CSE477 L07 Pass Transistor Logic.25
Irwin&Vijay, PSU, 2002
Differential TG Logic (DPL)
B
A
B
B
A
A
B
A
A
A
F=AB
GND
B
F=AB
A
B
B
GND
A
VDD
A
F=AB
B
VDD
A
B
B
AND/NAND
CSE477 L07 Pass Transistor Logic.26
F=AB
XOR/XNOR
Irwin&Vijay, PSU, 2002
Next Time: The MOS Transistor

MOS transistor dynamic behavior (R
and C)

Wire capacitance
CSE477 L07 Pass Transistor Logic.27
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Next Lecture and Reminders

Next lecture

MOS transistor dynamic behavior
- Reading assignment – Rabaey, et al, 3.2.3 & 3.3.3-3.3.5

Wiring capacitance
- Reading assignment – Rabaey, et al, 4.1-4.3.1

Reminders




Lecture 5! will be Thursday (guest lecturer)
Lecture 8 will be on the 24th and lectures 9+10 will be on the
26th
HW2 due September 24th; HW3 handed out then (due Oct
10th)
Evening midterm exam scheduled
- Wednesday, October 16th from 8:15 to 10:15pm in 260 Willard
- Only one midterm conflict filed for so far
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