Transcript CSE 477. VLSI Systems Design

CSE477
VLSI Digital Circuits
Fall 2003
Lecture 24: Memory Cell Designs
Mary Jane Irwin ( www.cse.psu.edu/~mji )
www.cse.psu.edu/~cg477
[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003
J. Rabaey, A. Chandrakasan, B. Nikolic]
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Review: Random Access Read Write Memories
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SRAM – Static Random Access Memory
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data is stored as long as supply is applied
large cells (6 fets/cell) – so fewer bits/chip
fast – so used where speed is important (e.g., caches)
differential outputs (output BL and !BL)
use sense amps for performance
compatible with CMOS technology
DRAM - Dynamic Random Access Memory
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periodic refresh required (every 1 to 4 ms) to compensate for the
charge loss caused by leakage
small cells (1 to 3 fets/cell) – so more bits/chip
slower – so used for main memories
single ended output (output BL only)
need sense amps for correct operation
not typically compatible with CMOS technology
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Review: 2D 4x4 SRAM Memory Bank
read
precharge
enable
bit line precharge
WL[0]
!BL BL
A1
WL[1]
A2
WL[2]
WL[3]
2 bit words
clocking and
control
A0
Column Decoder
sense amplifiers
BLi
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BLi+1
write circuitry
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6-Transistor SRAM Storage Cell
WL
off
M2
on
M4
Q
M5
!BL
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1
!Q
0
M6
M1
on
off
M3
BL
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SRAM Cell Analysis (Read)
WL=1
M4
M5 !Q=0
Q=1
M6
M1
Cbit
Cbit
!BL=2.5V  0

BL=2.5V
Read-disturb (read-upset): must limit the voltage rise on
!Q to prevent read-upsets from occurring while
simultaneously maintaining acceptable circuit speed and
area
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M1 must be stronger than M5 when storing a 1 (as shown)
M3 must be stronger than M6 when storing a 0
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Read Voltage Ratios
V!Q = [VDSATn + CR(VDD – VTn) - (VDSATn2(1+CR) + CR2(VDD – VTn)2)]/CR
where CR is the Cell Ratio = (W1/L1)/(W5/L5)  1.2
VDD = 2.5V
VTn = 0.4V

1.2
Voltage Rise on !Q
1
Keep cell size minimal
while maintaining read
stability
0.8
Make M1 minimum size
and increase the L of
M5 (to make it weaker)
0.6
- increases load on WL
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0.4
0.2

0
0
0.5
1
1.5
Cell Ratio (CR)
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2
2.5
3
Make M5 minimum size
and increase the W of
M1 (to make it stronger)
Similar constraints on
(W3/L3)/(W6/L6) when
storing a 0
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SRAM Cell Analysis (Write)
WL=1
M4
M5 !Q=0
M1
Q=1
0
M6
Cbit
Cbit
!BL=2.5V

BL=0V
The !Q side of the cell cannot be pulled high enough to
ensure writing of 0 (because M1 is on and sized to protect
against read upset). So, the new value of the cell has to
be written through M6.
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M6 must be able to overpower M4 when storing a 1 and writing a 0
M5 must be able to overpower M2 when storing a 0 and writing a 1
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Write Voltage Ratios
VQ = (VDD - VTn) –
((VDD – VTn)2 – 2(p/n)(PR)((VDD – |VTp|)VDSATp – VDSATp2/2))
where PR is the Pull-up Ratio = (W4/L4)/(W6/L6)  1.8
VDD = 2.5V
|VTp| = 0.4V
p/n = 0.5

0.5

0.4
Write Voltage (VQ)
Keep cell size minimal
while allowing writes

0.3
0.2
0.1
Make M4 and M6
minimum size
Be sure to consider
worst case process
corners (strong
PMOS, weak NMOS,
high VDD)
0
0
0.5
1
1.5
2
Pullup Ratio (PR)
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Cell Sizing and Performance
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Keeping cell size minimal is critical for large SRAMs
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Minimum sized pull down fets (M1 and M3)
- Requires longer than minimum channel length, L, pass transistors
(M5 and M6) to ensure proper CR
- But up-sizing L of the pass transistors increases capacitive load on
the word lines and limits the current discharged on the bit lines both
of which can adversely affect the speed of the read cycle

Minimum width and length pass transistors
- Boost the width of the pull downs (M1 and M3)
- Reduces the loading on the word lines and increases the storage
capacitance in the cell – both are good! – but cell size may be
slightly larger

Performance is determined by the read operation

To accelerate the read time, SRAMs use sense amplifiers (so
that the bit line doesn’t have to make a full swing)
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6-T SRAM Layout
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VDD
M2
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M4
M1
M3
GND
M5
BL
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M6
BL
WL
signal routing and connections
to two bit lines, a word line, and
both supply rails

Area is dominated by the
wiring and contacts (11.5 of
them)
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Other alternatives to the 6-T
cell include the resistive load
4-T cell and the TFT cell
neither of which are
available in a standard
CMOS logic process
Q
Q
Simple and reliable, but big
Irwin&Vijay, PSU, 2003
Multiple Read/Write Port Storage Cell
WL2
WL1
M2
M5
M4
!Q
Q
M7
M8
M1
!BL2

!BL1
M6
M3
BL1
BL2
To avoid read upset, the widths of M1 and M3 will have to
be sized up by a factor equal to the number of
simultaneously open read ports
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2D 4x4 DRAM Memory
read
precharge
enable
bit line precharge
WL[0]
BL
A1
WL[1]
A2
WL[2]
WL[3]
2 bit words
sense amplifiers
clocking,
control, and
refresh
BL0
A0
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BL1
BL2
BL3
write circuitry
Column Decoder
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3-Transistor DRAM Cell
WWL
WWL
RWL
VDD
BL1
M3
M1
X
M2
Cs
X
VDD-VT
RWL
read
BL2
V
Write: Cs is charged (or discharged) by asserting WWL and
BL1
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VDD-VT
BL2
BL1

write
Value stored at node X when writing a 1 is VWWL - VTn
Read: Cs is “sensed” by asserting RWL and observing BL2
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Read is non-destructive and inverting
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3-T DRAM Layout
BL2
BL1
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Total cell area is 576 2
(compared to 1,092 2
for the 6-T SRAM cell)
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No special processing
steps are needed (so
compatible with logic
CMOS process)
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Can use bootstrapping
(raise VWWL to a value
higher than VDD) to
eliminate threshold drop
when storing a “1”
GND
RWL
M3
M2
WWL
M1
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1-Transistor DRAM Cell
WL
WL
M1
X
X
write
1
read
1
VDD-VT
Cs
CBL
BL
BL
VDD/2
VDD
sensing
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Write: Cs is charged (or discharged) by asserting WL and
BL
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Read: Charge redistribution occurs between CBL and Cs
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Read is destructive, so must refresh after read
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1-T DRAM Cell Layout
Capacitor
Metal word line
M1 word
line
SiO2
poly
n+
Field Oxide
n+
poly
Inversion layer
induced by
plate bias
Diffused
bit line
Polysilicon
Polysilicon
plate
gate
(a) Cross-section
(b) Layout
Used Polysilicon-Diffusion Capacitance
Expensive in Area
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1-T DRAM Cell Observations
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Cell is single ended (complicates the design of the sense
amp)
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Cell requires a sense amp for each bit line due to charge
redistribution based read
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BL’s precharged to VDD/2 (not VDD as with SRAM design)
all previous designs used SAs for speed, not functionality
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Cell read is destructive; refresh must follow to restore
data
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Cell requires an extra capacitor (CS) that must be
explicitly included in the design
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not compatible with logic CMOS process
A threshold voltage is lost when writing a 1 (can be
circumvented by bootstrapping the word lines to a higher
value than VDD)
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Content Addressable Memories (CAMs)
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Memories addressed by their content. Typical
applications include cache tags and translation lookaside
buffers (TLBs) for virtual to physical address translation
Address issued by CPU (page size = index bits + word select bits)
Word in Line
2way Associative Cache
Cache Index
VA Tag
PA
Tag
Tag Data
Tag Data
PA Tag
Hit
Most TLBs are small
(<= 256 entries)
and thus fully associative
(CAM implementation)
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=
=
Hit
Desired word
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9-T CAM Cell
!BL
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Writes progress as in a
standard SRAM cell
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Compares the stored
data (Q and !Q) to the
bit line data
BL
WL
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Q
!Q
M3

M2
x
match
M1
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Precharged match line
ties to all cells in a row
If Q and BL match, x is
discharged through M2
and BL (data 0) or M3
and !BL (data 1) and thus
M1 is off keeping the
match line high
Else if Q and BL don’t
match, x is charged to
VDD – VT and match line
discharges thru M1
Irwin&Vijay, PSU, 2003
4x4 CAM Design
0 1
Hit
WL[0]
1
1
0
0
WL[1]
1
0
1
1
1
1
1
0
0
0
0
0
match[0]
1 0
match[1]
1 1
match[2]
1 0
WL[2]
WL[3]
to WL[0]
of data array
match[3]
1 0
Read/Write Circuitry
match/write data
1 011
precharge/match
0 1
CSE477 L24 RAM Cores.22
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Next Lecture and Reminders
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Next lecture
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Peripheral memory circuits
- Reading assignment – Rabaey, et al, 12.3-12.4
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Reminders
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HW#5 (optional) due December 2nd
Project final reports due December 4th
Final grading negotiations/correction (except for the final
exam) must be concluded by December 10th
Final exam scheduled
- Tuesday, December 16th from 10:10 to noon in 118 and 113
Thomas
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