Transcript 20040708yhhuang

Power Minimization using
Simultaneous Gate Sizing, Dual-Vdd
and Dual-Vth Assignment
Ashish Srivastava, Dennis Sylvester, David
Blaauw
Outline





Introduction
Preliminary
Algorithm
Experimental Results
Conclusions
Introduction
 Gate size => Delay Power
 VDD
=> Delay Power
 VTH
=> Delay Power
Outline
 Introduction
 Preliminary
 Dual Vdd constraint
 Cluster Voltage Scaling (CVS)
 Algorithm
 Experimental Results
 Conclusions
Dual Vdd Constraint
VDDH
VDDL
MP1
ON
1
0
Static current
N1
MN1
VDDL<VDDH-|Vtp|=>PMOS can not be cut-off
Cluster Voltage Scaling (CVS)
Level Converter
VDDH
i1
3
i2
i3
i4
i5
VDDL
1
5
2
4
LC
o1
9
LC
o2
10
LC
o3
LC
o4
8
6
7
Cluster Voltage Scaling (CVS)
Order by Capacitance or Slack
{O1,o2,o3,o4}
i1
1
5
3
i2
8
2
4
i3
6
7
i4
i5
VDDH
VDDL
o1
9
o2
10
o3
o4
Outline
 Introduction
 Preliminary
 Algorithm - VVS
 Backward Pass
 Frontward Pass
 Experimental Results
 Conclusions
Outline
 Introduction
 Preliminary
 Algorithm
 Backward Pass
 Frontward Pass
 Experimental Results
 Conclusions
Backward Pass
 Change cells from high VDD to low VDD
 Dual Vdd & single Vth
Backward Pass
 Step1 CVS
 without gate upsizing
 Step2
 with gate upsizing
Backward Pass
 Step1 CVS
8
4
6
1
2
5
7
VDDH
3
VDDL
Backward Pass
 Step 2
 Backward front
High Vdd
Gate Upsizing
8
4
6
7
1
Slack
2
5
3
1
D
Sensitivit
yVDDL 
VDDH
p arcs Slack arc  S min  k
Backward Pass
 Escape local minima. Find the globe
minima.
 The front between high and low Vdd gates
is in the best position in terms of the total
power dissipation for a dual Vdd, single Vth.
Outline
 Introduction
 Preliminary
 Algorithm
 Backward Pass
 Frontward Pass
 Experimental Results
 Conclusions
Forward Pass
Create timing
slack
Select a gate to high Vdd or upsizeing
Set gates to high Vth
Yes
Power Reduce?
Accept this move
No
Reverse this move
Forward Pass
 How to select a gate to high Vdd or to upsizing?
1
D
Sensitivity 

p arcs Slack arc  S min  k
Forward Pass
 How to select a gate to high Vth?
Slack arc
Sensitivity  P 
D
arcs
Outline





Introduction
Preliminary
Algorithm
Experimental Results
Conclusions
Experimental Results
% Savings compared to initial design
Initial Power (uW)
Circuit
Leakage
Switching
c432
35.4
81.7
c880
48.9
c1908
CVS only
Leakage
Switching
Leakage
Switching
117.1
0.50%
1.90%
1.50%
0.50%
140.1
188.9
20.60%
19.80%
20.00%
75.3
202.7
278
5.40%
5.60%
c2670
100
248.9
349
20.30%
c3540
131.6
302.6
434.2
c5315
210.9
413.8
c6288
544.3
c7552
214.9
Average
Total
Backward Pass
Total
VVS
Total
Leakage
Switching
Total
1.90%
1.50%
57.80%
6.00%
21.70%
20.60%
19.80%
20.00%
44.00%
22.90%
28.40%
5.50%
5.40%
5.60%
5.50%
44.10%
7.40%
17.40%
21.40%
21.10%
20.20%
37.80%
32.70%
20.20%
37.80%
32.70%
3.40%
6.50%
5.60%
2.80%
26.40%
19.20%
49.40%
26.10%
33.20%
624.7
21.20%
25.40%
23.90%
18.90%
50.50%
39.90%
19.00%
50.70%
40.00%
1716.2
2260.5
1.10%
15.70%
12.20%
1.00%
15.80%
12.20%
20.30%
19.40%
19.60%
521.4
736.3
30.20%
32.70%
32.00%
36.40%
50.80%
46.60%
36.60%
51.20%
46.90%
12.80%
16.10%
15.20%
13.20%
26.10%
22.20%
36.40%
27.70%
30.00%
Experimental Results
The nominal activity is adjusted such the leakage power constitutes
approximately 8% of the total power dissipation.
Experimental Results
Outline





Introduction
Preliminary
Algorithm
Experimental Results
Conclusions
Conclusions
 The VVS algorithm combines gate sizing
with Vdd and Vth assignment to minimize the
total power dissipation.