Transcript i(t) - Auburn University

ELEC 2200-002
Digital Logic Circuits
Fall 2014
Delay and Power
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]
Fall 2014, Nov 21
ELEC2200-002 Lecture 8
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Delay: Definitions
Rise time is the time a signal takes to rise from 10% to 90% of its
peak value.
Fall time is the time a signal takes to drop from 90% to 10% of its
peak value.
Delay of a gate is the time interval between the input crossing 50%
of peak value and the output crossing 50% of peak value.
VDD
90% VDD
B
1→1
1→0
10% VDD
GND
A
B
Fall time
NAND
gate
Time
C
Gate delay
0→1
VDD
90% VDD
C
GND
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Rise time
10% VDD
ELEC2200-002 Lecture 8
Time
2
Consider Delay of Inverter
(Other Gates are Similar)
VDD
Source
C1
In
1→0
Drain
0→1
Out → to fanout gates
Drain
C2
CW + C G-in
Source
GND
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ELEC2200-002 Lecture 8
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Capacitances in MOSFET
L = Channel length (fixed)
W = Width (transistor size)
tox = Oxide thickness
W
Cgs
Cgd
Gate
Gate oxide
Source
Drain
L
Cs
Cg
Bulk
Cd
R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design,
Boston: McGraw-Hill, 2008.
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ELEC2200-002 Lecture 8
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Gate Capacitance
Cg
Cpermicron
where
εox
=
εox WL / tox
=
Cpermicron W
εox
=
── L
tox
= 3.9ε0 for Silicon dioxide
= 3.9 × 8.85 × 10-14 F/cm
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ELEC2200-002 Lecture 8
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Propagation Delay of a Transition
Ron
VDD
ic(t)
vi (t)
vo(t)
CL
R = large
Ground
CL =
Total load capacitance for gate; includes transistor capacitances
of driving gate + routing capacitance + transistor capacitances
of driven gates; obtained by layout analysis.
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ELEC2200-002 Lecture 8
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Charging of a Capacitor
R = Ron
t=0
v(t)
i(t)
C = CL
VDD
Charge on capacitor, q(t)
=
C v(t)
Current, i(t)
=
C dv(t)/dt
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=
dq(t)/dt
ELEC2200-002 Lecture 8
7
i(t)
=
C dv(t)/dt =
dv(t)
∫ ───── =
VDD – v(t)
ln [VDD – v(t)] =
[VDD – v(t)] /R
dt
∫ ────
RC
–t
── +
RC
A
Initial condition, t = 0, v(t) = 0 → A = ln VDD
–t
v(t) = VDD [1 – exp(───)] = 0.5VDD
RC
t = 0.69 RC
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ELEC2200-002 Lecture 8
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Inverter: Idealized Input
INPUT
VDD
GND
Gate delay
OUTPUT
VDD
0.5VDD
GND
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time
t =0
0.69CR
ELEC2200-002 Lecture 8
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Large Circuit Timing Analysis
Determine gate delays:
From layout analysis, or use approximate delays:
– Gate delay increases in proportion to number of fanouts
(increased capacitance)
– Delay decreases in proportion to gate size increase
(reduced transistor channel resistance)
Purpose of analysis is to verify timing behavior –
determine maximum speed of operation.
Methods of analysis:
Circuit simulation – most accurate, expensive (Spice program)
Event-driven logic simulation – efficient, accurate
Static timing analysis (STA) – most efficient, approximate
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Static Timing Analysis (STA)
Combinational logic for critical path delays.
Circuit represented as an acyclic directed
graph (DAG).
Gates characterized by delays.
No inputs are used – worst-case analysis
– static analysis (simulation is dynamic).
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Example
Levelize graph. Initialize arrival times at primary inputs to 0.
0
0
A
1
H
3
Gate delay
0
0
0
0
0
0
Level 0
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B
3
E
1
G
2
C
1
J
1
F
1
D
2
1
Level of a gate is one greater than
the maximum of fanin gate levels
2
3
ELEC2200-002 Lecture 8
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5
12
Example (Cont.)
Determine output arrival time when all input arrival times are known.
0
0
0
0
0
0
0
0
Level 0
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A
1
1
Largest of input delays
+ gate delay
B
3
C
1
D
2
1
H
3
10
3
E
1
4
G
2
7
1
F
1
2
2
J
1
5
3
ELEC2200-002 Lecture 8
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8
5
13
Example (Cont.)
Trace critical path from the output with longest arrival time.
0
0
0
0
0
0
0
0
Level 0
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A
1
B
3
C
1
D
2
1
1
H
3
10
Critical path
Delay = 10
3
E
1
4
G
2
7
1
F
1
2
2
J
1
5
3
ELEC2200-002 Lecture 8
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8
5
14
Path Analysis Algorithms for Directed
Acyclic Graphs (DAG)
Graph size: n = |V| + |E|, for |V| vertices and |E|
edges.
Levelization: O(n) (linear-time) algorithm finds
the maximum (or minimum) depth.
Path counting: O(n2) algorithm. Number of paths
can be exponential in n.
Finding all paths: Exponential-time algorithm.
Shortest (or longest) path between two nodes:
– Dijkstra’s algorithm: O(n2)
– Bellman-Ford algorithm: O(n3)
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References
Delay modeling, simulation and testing:
– M. L. Bushnell and V. D. Agrawal, Essentials of Electronic
Testing for Digital, Memory and Mixed-Signal VLSI Circuits,
Springer, 2000.
Analysis and Design:
– G. De Micheli, Synthesis and Optimization of Digital Circuits,
McGraw-Hill, 1994.
– N. Maheshwari and S. S. Sapatnekar, Timing Analysis and
Optimization of Sequential Circuits, Springer, 1999.
PrimeTime (Static timing analysis tool):
– H. Bhatnagar, Advanced ASIC Chip Synthesis, Second Edition,
Springer, 2002
Fall 2014, Nov 21
ELEC2200-002 Lecture 8
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CMOS Logic (Inverter)
VDD
No current flows
from power supply!
Where is power
consumed?
GND
F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect
Metal-Oxide-Semiconductor Triodes,” IEEE International SolidState Circuits Conference Digest, vol. IV, February 1963, pp.
32-33.
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Components of Power
Dynamic, when output changes
– Signal transitions (major component)
Logic activity
Glitches
– Short-circuit (small)
Static, when signal is in steady state
– Leakage (used to be small)
Ptotal =
=
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Pdyn + Pstat
Ptran + Psc + Pstat
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Charging of Output Capacitor
From Slide 8:
v(t) =
i(t)
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=
–t
V [1 – exp( ── )]
RC
dv(t)
C ───
dt
=
V
–t
── exp( ── )
R
RC
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Total Energy Per Charging
Transition from Power Supply
Etrans =
=
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∞
∫ V i(t) dt =
0
CV
∞ V
2
–t
∫ ── exp( ── ) dt
0 R
RC
2
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Energy Dissipated Per Transition in
Transistor Channel Resistance
∞2
R ∫ i (t) dt
0
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=
V ∞
-2t
R ──
∫ exp( ── ) dt
2
R 0
RC
=
1
2
─ CV
2
2
ELEC2200-002 Lecture 8
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Energy Stored in Charged Capacitor
∞
∞
-t V
-t
∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt
0
0
RC R
RC
1
2
= ─ CV
2
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ELEC2200-002 Lecture 8
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Transition Power
Gate output rising transition
2
– Energy dissipated in pMOS transistor = CV /2
2
– Energy stored in capacitor = CV /2
Gate output falling transition
2
– Energy dissipated in nMOS transistor = CV /2
2
Energy dissipated per transition = CV /2
Power dissipation:
Ptrans =
α
Fall 2014, Nov 21
Etrans α fck =
2
α fck CV /2
=
activity factor
fck = clock frequency
ELEC2200-002 Lecture 8
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Components of Power
Dynamic
– Signal transitions
2
0
Delay
=1
Logic activity
Glitches
– Short-circuit
Static
– Leakage
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GLITCH
Delay=2
1
3
0
Ptotal =
=
Pdyn + Pstat
Ptran + Psc + Pstat
ELEC2200-002 Lecture 8
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Short Circuit Power of a Transition: Psc
VDD
vi (t)
isc(t)
vo(t)
CL
Ground
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Short-Circuit Power
Increases with rise and fall times of input.
Decreases for larger output load
capacitance; large capacitor takes most of
the current.
Small, about 5-10% of dynamic power;
momentary shorting of supply and ground
during opening and closing of transistor
switches.
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Components of Power
Dynamic
– Signal transitions
Logic activity
Glitches
– Short-circuit
Static
– Leakage
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Static (Leakage) Power
Reason: Resistance of an open transistor switch
is large but not infinite.
Leakage power as a fraction of the total power
increases as clock frequency drops. Turning
supply off in unused parts can save power.
For a gate it is a small fraction of the total power;
it can be significant for very large circuits.
Static power increases as feature size is scaled
down; controlling leakage is an important aspect
of transistor design and semiconductor process
technology.
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ELEC2200-002 Lecture 8
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CMOS Gate Power
R = Ron
V
i(t)
vi (t)
Large
resistance
v(t)
Output signal
transition
v(t)
i(t)
Dynamic
current
isc(t)
Short-circuit
current
C
isc(t)
Ground
Leakage
current
Leakage
current
time
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