Transcript 슬라이드 1 - KAIST

Background for
Leakage Current
Sept. 18, 2006
Power Challenge
 Active power density increasing with
device scaling and increased frequency
 Leakage power density increasing due
to lower Vt and gate leakage
 Stressing packaging, cooling, battery
life, etc.
 Complicates IDDq testing as well
Source from Bergamaschi
Thinning gate oxides
increase
gate tunneling leakage
Problem Statement
• Power Analysis on CMOS Inverter
Input switching to '1' or '0'
Vthn < Input < VDD-|Vthp |
Input : '1' or '0' steady state
charge
Input
Input
Input
Cload
discharge
(a) Capacitive Current
(b) Short Circuit Current
(c) Static Leakage Current
Problem Statement
• Dynamic Power
Pswitching  Cswitching VDD2  f
• Average Short Circuit Current
I SC 
  in
12 VDD
 (VDD  2Vth ) 3  f
gain _ factor: n  p   ,
Threshold _ Voltage: Vthn  Vthp  Vth
• Sub-threshold Leakage Current
I DS    e(VGS Vth )q / nkT  (1  eVDS q / kT )
K: function of technology, VGS : gate  to  source voltage, VDS : drain  to  source voltage,
Vth : theshold voltage, q: electronic charge, k : Boltzmann constance, T: temperature,
n: nonlinearity constance 1 ~ 2 , ( kT  0.0259)
Problem Statement
• Domination of Leakage Current
Feature Size
> 0.25um
0.18/0.13/0.09um…
Performance(AP)
< 200MHz
300/400/533MHz, 1GHz
Core Voltage
5.0/3.3/2.5V
1.8/1.2/1.0V …
VTH(Threshold)
> +/- 0.6V
+/- 0.5, 0.4, 0.3V …
TR Leakage
Negligible
Exponential growing(SD/Gate)
Stand-by Mode
PLL-off(Clock-off)
V/MTMOS, High VTH/High VDD
Low Power
Focus on Operating Power
Focus on Operating/Stand-by
Active and Leakage Power with CMOS
Scaling
• As CMOS scales down the
following stand-by leakage
current rises rapidly.
– Source to drain leakage
(diffusion+tunneling) as
Lg scales down
– Gate leakage current
(tunneling) as Tox scales
down
– Body to drain leakage
current (tunneling) as
channel doping scales
up
Two cases of Leakage Mechanism
Turn off
Turn on
Sub-threshold Leakage
Source to drain tunneling
Vg=0V
Vd=Vdd
Drain to Body tunneling (BTB)
Vg=Vdd
Vd=0V
Gate oxide
tunneling
2
Current Density (A/cm)
Gate Leakage Current Reduction with
High-K Gate Dielectric
1
10
0
10
-1
10
Drain leakage
-2
10
-3
10
Gate leakage
High-K gate dielectric
-4
10
Cox 
-5
10
k0 A
Tphysical
-6
10
20
25
30
Tox (A)
35
40
Voltage Scaling for Low Power
Low Power
P  VDD2
Low VDD
I ds  (VDD - Vth)1~2
Low Speed
Speed Up
I leakage  e-C x Vth
Low Vth
High Leakage
Leakage
Suppression
I ds  (VDD - Vth)1~2
Low-Leakage Solution – Technology
100m
VTH control
Dynamic power[W]
VDD control
10m
High speed
MTCMOS
High speed
VDD: 1.5V
VDD control
1m
VDD: 1.0V
Low speed
VTH control
Low speed
VTH: 0.5V
100n
1p
10p
VTH: 0.25V
100p
1n
10n
Leakage power[W]
100n
VTCMOS & MTCMOS
Multi-Threshold CMOS
Variable-Threshold CMOS
Schematic Diagram principle Merit
VDD
VDD
Low-Vth
Sleep
Hi-Vth
N-well
Low Vt
GND
P-well
Vpb = VDD
or V+
Vt
Control
circuit
Vnb = 0 or V-
GND
•On-off control of internal
VDD or VSS
•Special F/Fs, Two Vth’s
•Threshold control with bulk-bias
•Triple well is desirable
•Low leakage in stand-by mode.
•Conventional design Env.
•Low leakage in stand-by mode.
•Conventional design Env.
Demerit
•Large serial MOSFET
•ground bounce noise
•Ultra-low voltage region?(1V)
•Scalability? (junction leakage)
•TR reliability under 0.1mm
•Latch-up immunity, Vth controllability,
Substrate noise, Gate oxide reliability
•Gate leakage current
MTCMOS : Reduce Stand-by Power with
High Speed
With High VTH switch (MTCMOS)
Without High VTH switch
Vdd
Vdd
Normal or Low VTH MOSFET
0
0
1
1
Virtual Ground
Vss
0
Vss
High VTH switch
• With High VTH switch, much lower leakage current flows
between Vdd and Vss
• High VTH MOSFET should have much lower ( >10X) leakage
current compared to normal VTH MOSFET
Multi-Threshold CMOS (MTCMOS)
• Mobile Applications
– Mostly in the idle state
– Sub-threshold leakage Current
• Power Gating
– Low VTH Transistors for High Performance Logic
Gates
– High VTH Transistors for Low Leakage Current
Current
Gates
Logic
Component Cutoff-Switch
(High Vth)
(Low Vth)
Operating
Mode Active Sleep
Sleep
Control
(SC)
VDD
Low Vth
MOS
Active
SC
Time
VGND
VSS
High Vth
MOS
CCS Sizing
• The effect of CCS (current-controlled switch) size
– As the size decreases, logic performance also
decreases.
– As the size increases, leakage current and chip
area also increase.
– Proper sizing is very important.
– CCS size should be decided within 2%
performance degradation.
VDD
Low Vt
Switch
Control
High Vt
GND
Vop = VDD - V
V must be sized
within 2% performance degradation
.
Leakage Current :
Limiting Factor in VDSM
Technology
C.M.Kyung
ITRS roadmap
• Scaling down allows the same performance with
reduced voltage, leading to low power.
• From 0.18 micron down, building a transistor with a
good active current(Ion) and a low leakage current (Ioff)
is difficult.
– high-speed TR’s ; low channel doping
– low-leakage TR’s ; high channel doping
• Now three groups of TR’s;
– High Performance (HP) ; high active current ; Thin Tox
– Low Operating Power (LOP) ; low active current ; High Tox
– Low Standby Power (LSTP) ; low static current ; High Tox
Device characteristics for HP, LOP, and LSTP Technologies
Bulk CMOS vs. SOI
• Buried oxide layer below active silicon
layer -> electrical isolation of TR’s
– Lower parasitic cap.
• PD(Partially Depleted)
– Floating body effect increases speed
• Low threshold in dynamic mode
• or FD(Fully Depl)
– Ideal subthresold swing of 60 mV/decade
Reducing Subthreshold current in
Bulk CMOS
• VTCMOS (Variable Threshold)
– Tune substrate bias to adjust Vth
– Requires efficient DC-DC converter
– For a given technology, there an optimum in VR , as
decreasing subthreshold leakage is accompanied by an
increase in drain junction leakage
• When both High Vt and Low Vt TR’s are available,
– MTCMOS (Multi-Threshold) ; Introduce high Vt power switch
to limit leakage in stby mode
– Use low Vt for critical path
– This can be coupled with multiple VDD’s
• Other tricks
– Set up the logical internal states where the total leakage is
minimal.
Five types of off-currents
• Tunneling through gate oxide
– Fowler-Nordheim tunneling -> direct tunneling
• Subthreshold current
• Gate-induced drain leakage (GIDL)
– Thermal emission
– Trap-assisted tunneling
– BTBT
• Reverse-biased pn junction current
– -> band-to-band tunneling (BTBT) current
• Bulk punch-through
Gate-induced drain leakage
(GIDL)
• Gate-induced drain leakage (GIDL)
– Thermal emission
– Trap-assisted tunneling
– BTBT
• Fig 3.12
Leakage current due to
QM Tunneling
• substrate and drain ; band-to-band
tunneling ;
– increases with E-field and dopant concentration
due to scaling
• source and drain ;
– Surface punchthru due to DIBL
– Punch-through at bulk
• gate oxide ;
– SiO2 has been used as it has so low trap and
fixed charge density at the interface
– Gate current is an exponential function of Tox and
Vox
– Hole tunneling is 10% of that of electron due to
higher barrier height and heavier effective mass
Gate Leakage Current Reduction with
High-K Gate Dielectric
• As Tox scales gate leakage current increases
exponentially due to exponential increase of
tunneling probability with reduction of physical
tunneling distance.
• Physically thicker gate dielectric allows lower
leakage current but lower oxide capacitance
reducing on-current
• Using high k (dielectric constant) material, both
thicker physical thickness and higher oxide
capacitance can be achieved.
• Applying high-k gate dielectric, several orders of
magnitude lower gate leakage current can be
achieved with similar oxide capacitance
Approach 1 to reduce gate
leakage ; High K materials
• To suppress gate tunneling current, use
materials with
– High K -> increases thickness (t)
– Higher barrier height (h)
• Using high K
– Increases short-channel effects due to thicker
gate dielectric (This sets an upper limit on K, lower
limit coming from I tunnel)
– Mobility degradation due to poor interface quality
Approach 2 to reduce gate leakage ; stop
scaling the thickness of gate oxide
• Thicker gate oxide yields less control of
gate on channel conduction, i.e., higher
short-channel effects and DIBL effects.
Approach 3 to reduce gate leakage
• Multiple gates allows better control of
channel by gate, and lets scaling continue
without excessive short-channel effects
–
–
–
–
Double gate
FinFET
Triple gate
Quadruple or gate all-around