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Threshold Voltage Assignment to Supply Voltage Islands in Corebased System-on-a-Chip Designs Project Proposal: Gall Gotfried Steven Beigelmacher 02/09/05 Overview Introduction Related Work Design Space What has already been done What we plan to do Milestones Deadlines we intend to keep Introduction Trends in Design As process technology improves, more devices will be integrated onto a chip, designs will grow more complex The scope of future designs will increasingly make SoC attractive Importance of Low Power Despite what designers previously thought, the power problem has not been solved Need proven techniques that will continue to be effective with future technology nodes Vdd and Vth assignment Introduction Need low power techniques that work in an SoC framework An SoC design: Hard and soft IP blocks that have been independently characterized The number of blocks may range from a handful up to one hundred There may already be an initial placement of blocks within a defined die size We probably don’t have the freedom to tweak parameters within a core Low power techniques must exist at the intracore level Introduction Voltage islands are regions where nearby IP blocks may use a supply voltage different from the full-chip supply We propose taking voltage islands in a corebased SoC design, and adding Vth assignments and latency measures It looks a lot like a placement problem (simulated annealing, quadratic placement, etc) Related Work Reduction of power in a system-on-chip Set number of cores Set die size Tool used to move around cores based on common supply voltage These common core sections are referred to as voltage islands Cores have several operating supply voltages Algorithm finds optimal placement of cores Related Work Algorithm considers in placement Wire lengths Minimizes the length of wires between cores Minimum number of islands Reduces the number of voltage converters More Related Work Fine grained supply and threshold voltage selection Gate level partitioning instead of core based Balance between Vdd and Vth is kept to maintain maximum performance Frequency island partitioning Cores are partitioned based on minimum operating frequency Reduces clock skew Communication queues are required for inter-core operations Design Space Code exists to take an initial placement and create a placement maximizing the use of voltage islands (Vdd only) First step is implement algorithm from previous voltage island paper and attempt to match results But we can’t get access to it Still unsure about implementation approach: Simulated annealing, integer linear programming, topological heuristic, etc Also need to generate comparable benchmarks Then our work really begins Design Space Need to extend baseline implementation to handle Vth assignment Examining multi-pass solutions (first assign Vdds, then Vth, and so on – or start with Vth) Concern about convergence using a single solution pass via simulated annealing Need to take the latencies of IP blocks into account If time permits, we hope to evaluate a few alternative solutions for comparison Milestones Previous work exploration Extend Algorithm Begin implementing algorithm for Vdd island partitioning Deadline 02/23/2005 Test benchmarks on Vdd algorithm to attain similar results as paper suggests Begin extending algorithm to include optimum Vth assignment Deadline 03/21/2005 Achieve Results Test algorithm performance on benchmarks used in Vdd only algorithm Deadline 04/11/2005 You Got Questions We Got Answers