Transcript CURRENT MIRRORS Principle

CURRENT
MIRROR/SOURCE
EMT451/4
DEFINITION
Circuit that sources/sinks a constant
current
as biasing elements
as load devices for amplifier stages
CURRENT MIRRORS
Principle : if the G-S potentials of two
identical MOS transistors are equal, the
channel currents should be equal.
Mathematical perspective:
ID = f(VGS)=Iref for a MOSFET -> hence VGS = f-1(ID)=f-1(Iref)
i.e. apply VGS, get Iref, or transistor biased at Iref produces VGS
If the same voltage is applied to G and S of a second
MOSFET, then ID=Iout=f(VGS)=f[f-1(Iref)]=ff-1Iref=Iref
Another way of saying it: if we have two MOS devices with
equal VGS in saturation, then they will carry equal currents
BASIC CURRENT MIRROR
VDD
R
IREF
Io
M1
M2
 The most basic current mirror circuit consists of 2
matching MOSFET transistors connected back to back,
such that both have the same Gate-to-Source voltage.
BASIC CURRENT MIRROR (cont’d)
Given:
(*) The two enhancement-type NMOS transistors have
matching features, as follows: VTH,1 = VTH,2 , kn,1’ = kn,2’,
λ1 = λ2 =0
(*) “By structure” we have that VGS,1 = VGS,2
(*) Typically the supply VDD, resistor R and a desired
reference current IREF are all given.
(*) The ratio (W/L)1 is not necessarily equal to the ratio
(W/L)2
(*) “By structure” we have that VGD,1 = 0, and because the
transistor is an enhancement-type, this guarantees that
transistor 1 is always in Saturation Mode
BASIC CURRENT MIRROR (cont’d)
VDD
R
IREF
Io
M1
M2
Need: Using the
transistors geometries
(W/L)1 and (W/L)2 as
design parameters, we
want to create a DC
current Io, as long as
transistor M2 is in
Saturation Mode
BASIC CURRENT MIRROR (cont’d)
 The Drain of transistor M2 is
connected to a load circuit, not
necessarily a resistor. The load
circuit typically involves one or
more additional MOSFET
transistors. Depending on the
load, transistor M2 may be in any
of three modes: Saturation,
Triode or Cutoff. Of course, only
when it is in Saturation it will work
as originally planned (a DC
current source)
VDD
R
IREF
Io
M1
M2
BASIC CURRENT MIRROR (cont’d)
VDD
R
IREF
Io
M1
M2
 The current Io always goes away from the load
circuit and into M2. Such a DC current source is
said to be a sink.
Design of a Current Mirror DC Sink
VDD
We shall look first at M1:
R
I D1  I REF

1
W
 k n ,1 ' ( )1 (VGS ,1  VTH ,1 ) 2
2
L
VDD  VGS ,1
IREF
Io
M1
R
So, indeed if IREF is specified and VDD and R are given,
then by the right-hand term the needed voltage VGS,1 is
specified. Then, using the middle term, need to solve
for (W/L)1.
M2
VDD
Example 1:
20μA/V2
Let VDD = 5V, VTH,1 = 1V, kn,1' =
and R = 1KΩ.
What should be (W/L)1 needed for
creating IREF = 1mA?
I REF  1mA 
 I REF  1mA 
(
W
)1  11.11
L
VDD  VGS ,1
R

5  VGS ,1
1
R
IREF
Io
M1
 VGS ,1  4V
1
W
1
W
k n ,1 ' ( )1 (VGS ,1  VTH ,1 ) 2   20 10 3 ( )1 (4  1) 2 
2
L
2
L
M2
Let us now focus our attention on the "mirror" transistor M2:
VDD
R
IREF
ID1
IO
+
ID2
IO
M2 +
VO
-
M1
VO
-
Neglect CLM   = 0
I REF
1
W 
2
 I D1  nCox   VGS ,1  VTH ,1 
2
 L 1
IO  I D2 
1
W 
nCox   VGS , 2  VTH , 2 2
2
 L 2
We now divide the two equations
and use all the given matching
parameters of the two transistors.
IO
I REF

W / L 2

W / L 1
Example 2 (Follow-up to Example 1)
What should be (W/L)2
if we want Io = 7mA?
Solution
By Example 1 we have
that IREF = 1mA and
(W/L)1
=
11.11.
Therefore:
Io
I REF
VDD
R
IREF
Io
M1
W
W
( )2
( )2
7mA
W
L
L



 ( ) 2  77.77
W
1mA 11.11
L
( )1
L
M2
Question:
What do we do if we want to create a source DC current
source, rather than a sink ?
[A "source" is when the current goes from the current
source into the load circuit]
Answer:
If we build a current mirror current source using PMOS
transistors (rather than NMOS) then the output DC current
will be "sourced" and not "sunk".
Question:
If we need to generate multiple different DC current
sources and sinks, what is the total number of resistors
needed for the design?
Answer:
Just one resistor for the entire circuit!
Current Steering
VDD
VDD
M4
M5
VDD
IREF
R
M1
I2
I4
I5
M2
I3
M3
-VSS
-VSS
-VSS
The use of a negative DC supply –VSS does not change the
fact that, by-structure, both transistors, in every mirror pair,
have the same VGS voltage.
Recalculation of Reference Current
VDD
VDD
M4
M5
VDD
IREF
R
I2
I4
M1
I5
M2
I3
M3
-VSS
I D,1  I REF
-VSS
-VSS
VDD  (VSS  VGS ,1 )
1
W
2
 kn,1 ' ( )1 (VGS ,1  VTH ,1 ) 
2
L
R
NMOS Current Mirror Sinks:
VDD
VDD
M4
M5
VDD
IREF
R
I2
I4
M1
I5
M2
I3
M3
-VSS
-VSS
-VSS
I2
I REF
W
( )2
 L
W
( )1
L
I3
I REF
W
)3
 L
W
( )1
L
(
Current Steering Mechanism:
VDD
VDD
M4
M5
VDD
IREF
R
M1
I2
I4
I5
M2
I3
M3
-VSS
-VSS
-VSS
The Drain current of the NMOS transistor M3 comes from
the Drain of the PMOS transistor M4.
I 4 = I3
Can "steer" a current from NMOS current mirror to PMOS
current mirror, or vice versa.
Current Steering Mechanism:
V
DD
VDD
M4
M5
VDD
IREF
R
M1
I2
I4
I5
M2
I3
M3
-VSS
-VSS
-VSS
There is no need for the NMOS and PMOS to be matching:
Only all the NMOS transistors must match among
themselves, and the PMOS transistors must be mutually
matching.
PMOS Current Mirror
VDD
VDD
M4
M5
VDD
IREF
R
M1
I2
I4
I5
M2
I3
M3
-VSS
-VSS
-VSS
W
( )5
I5
 L
W
I4
( )4
L
For the PMOS transistors M4 and M5, the following
parameters must match:
VTH,4 = VTH,5 , kp,4’ = kp,5’, λ4 = λ5
We can now relate the sourced current I5
to the reference current IREF:
I5
I REF

I3
I REF
I5
I REF
W
W
( )3
( )5
I4 I5
   L 1  L
W
I 3 I 4 (W )
( )4
1
L
L
W
W
( )3 ( )5
 L  L
W
W
( )1 ( ) 4
L
L
Summary:
1) We need only one resistor R, no matter how
large is the number of DC currents
generated.
2) By using current steering we can create
sourcing currents from sinking currents or
vice versa.
3) The reference current can reside either in
a NMOS current mirror or in a PMOS
current mirror.
Example ( a follow-up to the previous example)
Given: VDD = 5V, VSS = 0
VTH,1 = VTH,2 = VTH,3 = 1V, kn,1' = kn,2'=kn,3'= 20μA/V2
and R = 1KΩ.
VTH,4 = VTH,5 = -1V, kp,4' = kp,5'= 30μA/V2
Need: A reference current of IREF = 1mA, one sink
current of 7mA and one source current of 5mA.
Question: Using the diagram scheme just
discussed, what should be all (W/L) ratios of all five
transistors?
Solution:
The beginning of the solution is identical to what has
been done in the previous examples.
Let's quote the results:
(W/L)1 = 11.11 and (W/L)2 = 77.77mA.
Current I2 is then the desired sink current VDD
VDD
VDD
IREF
R
M1
M4
I2
I4
I5
M2
I3
M3
-VSS
M5
-VSS
-VSS
Now:
I5
I REF
W
W
W
W
( )3 ( )5 ( )3 ( )5
5mA

 L  L  L  L
1mA (W ) (W )
11.11 (W )
1
4
4
L
L
L
There are infinitely many choices for the geometric
dimensions of transistors M3, M4 and M5. For
instance, we may take (W/L)3 = 11.11, (W/L)4 = 10
and (W/L)5 = 50. Current I5 is then the required
source current.
The channel-length modulation effect may be
responsible for errors in the operation of a Current
Mirror Current Source.
For instance, depending on the load of M2 we may
get VDS,2 ≠ VDS,1. As a result the value of I2 will
slightly vary, depending on the load. It means that the
current source is not ideal - it has a finite output
resistance, equal to ro of the respective output
transistor.
MULTIPLE CURRENT MIRROR
 Since there is no gate current in a MOSFET, a number of
MOSFETs can be connected to a single reference
MOSFET M1. Different output currents can be obtained
by suitably adjusting the width-to-length ratios of
MOSFETs (i.e. M2 and M3). In practice, the gate length, L
is normally kept constant and the gate width, W of M2,
M3, and M4 gives the relationship of the output currents
I2, I3, and I4 to IR as I2 = (W2 /W1)IR, I3 = (W3 /W1)IR, and I4
= (W4 /W1)IR
 The small-signal output resistance of the current source
is, Ro = rds1 = 1/ID1
MULTIPLE CURRENT MIRROR
CASCODE CURRENT MIRROR
Using KVL and the relation v gs1   ro 2 i x , we get
v x  ro1i1  ro 2 i x  ro1 (i x  g m1v gs1 )  ro 2 i x  ro1 (i x  g m1ro 2 i x )  ro 2 i x
which gives the output resistance RO of the current source as
RO  ro1 (1  g m1ro 2 )  ro 2
For identical transistors, ro1  ro 2  ro andRo becomes
RO  ro1 ( 2  g m1ro )  g m1ro2
WILSON CURRENT MIRROR
v gs 3 
ix
and v gs1  v gs 3   g m 3 v gs 3 ro 3
gm2
v gs1  (1  g m 3 ro 3 )v gs 3  (1  g m 3 ro 3 )
ix
gm2
WILSON CURRENT MIRROR
Applying KVL , we get
v x  (i x  g m1v gs1 ) ro1 
ix
gm2
which, after substituting for
v gs1
and simplifying, gives
the output resistance RO as
RO 
vx
1
g
 ro1 
 m1 ro1 (1  g m 3ro 3 )
ix
gm2 gm2
 ro1  ro1 (1  g m 3ro 3 )
for g m1  g m 2  g m 3
The drain voltages VD1 and VD 3 of M 1 and M 3 are unequal. Therefore,
drain currents I D1 and I D 3 are also unequal. This problem can be
solved by adding one diode-connected MOSFET.