Transcript slides10 - TAMU Computer Science Faculty Pages

The Processor 2
Andreas Klappenecker
CPSC321 Computer Architecture
The Processor: Datapath and Control
We want to implement portions of MIPS
 memory-reference instructions: lw, sw
arithmetic-logical instructions:
add, sub, and, or, slt
 control flow instructions: beq, j

We ignore multiply, divide, and other integer
and floating point instructions.
Implementation Details

Abstract, simplified view
Data
Register #
PC
Address
Instruction
memory
Instruction
Registers
Register #
ALU
Address
Data
memory
Register #
Data
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Two types of functional units:
 elements that operate on data values (combinational)
 elements that contain state (sequential)
Five Execution Steps
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Instruction Fetch
Instruction Decode and Register Fetch
Execution, Memory Address Computation,
or Branch Completion
Memory Access or R-type instruction
completion
Write-back step
Instruction Fetch
Instruction
address
PC
Instruction
Add Sum
Instruction
memory
a. Instruction memory
b. Program counter
c. Adder
 Use PC to find new instruction
 PC = PC + 4, preparing for next instruction
Instruction Fetch + PC update
R-Format Instructions
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Register format
op-code
6
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rs
rt
5
rd
5
shamt
5
5
op: basic operation of instruction
funct: variant of instruction
rs: first register source operand
rt: second register source operand
rd: register destination operand
shamt: shift amount
funct
6
Implementing R-Format Instructions
5
Register
numbers
5
5
Data
3
Read
register 1
Read
register 2
Registers
Write
register
Write
data
ALU control
Read
data 1
Data
Zero
ALU ALU
result
Read
data 2
RegWrite
a. Registers
b. ALU
 R-Format ALU operations need the register file
 and an implementation of the ALU
Register File
Read register
number 1
Read
data 1
Read register
number 2
Register file
Write
register
Write
data

Read
data 2
Write
Built using D flip-flops
Reading the Register File
Read register
number 1
Register 0
Register 1
Register n – 1
M
u
x
Read data 1
M
u
x
Read data 2
Register n
Read register
number 2
Multiplexers select the outputs
D flip-flop
Output changes only on falling clock edge
D
D
C
D
latch
Q
D
Q
D
latch _
C
Q
Q
_
Q
D
C
C
Q
Writing into the Register File
Write
0
Register number
C
Register 0
1
D
n-to-1
decoder
C
n– 1
Register 1
D
n
C
Register n – 1
D
C
Register n
Register data


D
log n+1 input bits address n+1 registers
Falling edge of clock signal determines when
to write
Implementing Loads and Stores
MemWrite
Address
Write
data
Read
data
Data
memory
16
Sign
extend
32
MemRead
a. Data memory unit
b. Sign-extension unit
Register file, ALU, data memory unit, sign extension unit
Datapath for a load and store
1.
2.
3.
4.
register access
memory access calculation
read or write from memory
in the case of a load, write into register file
Datapath for a Branch
Use ALU to evaluate the branch condition, another adder for
branch target = PC + 4 + (sign extended 16 bits)>>2
Summary
 Found implementations for R-format instructions
 Found implementations for loads and stores
 Found implementations for branches
 We need to compose these datapaths
 Simplicity of the implementations is striking!