Transcript oldchapter5part2

CS/COE0447
Computer Organization &
Assembly Language
Chapter 5 Part 2
1
Fig 5.17
2
Control Unit
• Implements (in hardware) an if statement:
– If opcode == 000000 # r-type instruction
•
•
•
•
MemWrite = 0
MemRead = 0
MemToReg = 0
… # values assigned for all the control unit’s output signals
– Elif opcode == 0x23 # lw
•
•
•
•
MemWrite = 0
MemRead = 1
MemToReg = 1
…
– Elif opcode == 0x4 # beq
•
•
•
•
MemWrite = 0
MemRead = 0
MemToReg = X
…
# don’t care
– … # an Elif test for each opcode
3
Examples
• In Lab 10, you did examples for an R-type
instruction and for sw
• Now, let’s look at examples for beq and lw
4
Instruction Execution (reminder)
• beq
– Fetch instruction and add 4 to PC beq $t0,$t1,L
• Assume that L is +3 instructions away
– Read two source registers $t0,$t1
– Sign Extend the immediate, and shift it left by 2
• 0x0003  0x0000000c
– Perform the test, and update the PC if it is true
• If $t0 == $t1, the PC = PC + 0x0000000c
• [we will follow what Mars does, so this is not
Immediate == 0x0002; PC = PC + 4 + 0x00000008]
5
0x10010000: Beq $t0,$t1,L
L == 1001000c
Fig 5.17
000100
000100
000100
000100
000100
000100
000100
000100
000100
000100
000100
6
Example: lw r8, 32(r18)
I-Format
• Let’s assume r18 has 1,000
• Let’s assume M[1032] has 0x11223344
7
Example: lw r8, 32(r18)
(PC+4)
(PC+4)
Branch=0
35
RegWrite
(PC+4)
18
8
RegDest=0
8
0
0x11223344
1000
0x11223344
ALUSrc=1
32
1032
MemtoReg=1
32
32
MemRead
0x11223344
8
Control Sequence for lw
• OPcode = 35
– RegDst = 0
– ALUSrc = 1
– MemtoReg = 1
– RegWrite = 1
– MemRead = 1
– MemWrite = 0
– Branch = 0
– ALUop = 0
9
Fig 5.17 (for reference)
10
Control Signal Table Fig 5.18
Figure 5.18 shows the control-signal information for Fig 5.17.
Figure 5.16 describes each of these signals, with one mistake:
“PCSrc” in 5.16 should be “Branch”
11
ALU Control HERE!!
• Depending on instruction, we perform different
ALU operations
• Example
– lw or sw: ADD
– and: AND
– beq: SUB
• ALU control input (3 bits) (page 301)
–
–
–
–
–
000: AND
001: OR
010: ADD
110: SUB
111: SET-IF-LESS-THAN (similar to SUB)
12
ALU Control (figure 5.12)
• ALUop
– 00: lw/sw, 01: beq, 10: arithmetic, 11: jump
13
ALU Control Truth Table Fig 5.13
14
ALU Control Logic Design we’ll return
to this when we cover appendix B
15
Datapath w/ Jump Fig 5.24
16
What We Have Now Fig 5.24
17
Functional Units Used
18
Single-Cycle Execution Timing
(in pico-seconds)
19
Single-Cycle Exe. Problem
• The cycle time depends on the most timeconsuming instruction
– What happens if we implement a more
complex instruction, e.g., a floating-point mult.
– All resources are simultaneously active –
there is no sharing of resources
• We’ll adopt a multi-cycle solution
– Use a faster clock
– Allow different number of clock cycles per
instruction
20
A Multi-cycle Datapath
• A single memory unit for both instructions and data
• Single ALU rather than ALU & two adders
• Registers added after every major functional unit to hold
the output until it is used in a subsequent clock cycle
21
Multi-cycle Approach
• Reusing functional units
– Break up instruction execution into smaller steps
– We’ll need more and expanded MUX’s
• At the end of a cycle, keep results in registers
– Additional registers
• Now, control signals are NOT solely determined
by the instruction bits
• Controls will be generated by a FSM!
22