Transcript EE595_Team3_P2_Fall07

Depth Finder 600
EE 595 Capstone Design Project
Fall 2007
Team 3
1
Team #3: Group Members
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Adam Davis
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Tony Johnson
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Peter Meyer
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Isaac Krull
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Joe Reisinger
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Expertise: Digital: PLD/FPGA VHDL
Experience: Associate Applications Engineer @ Rockwell
Expertise: Microprocessors
Experience: Part Time Design Engineer @ Bucyrus
Expertise: Management Skills
Experience: Soldering, Hands-On
Expertise: Calibration, C++ Programming
Experience: Engineering Intern @ Johnson Controls
Expertise: PDP, Reliability
Experience: Systems Engineer @ Baxter Health Care
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Depth Finder
•
This product uses a power supply, receiver, transmitter, microprocessor and
user interface.
•
This application specific design will relieve the end user of difficult and hard
to understand interfaces while still maintaining reliability for marine
applications
•
This system will use a 12VDC power supply designed for marine use or 8 D
Cell batteries.
•
This is a relatively simply design with 5 separate blocks. It utilizes our
strengths as a team while still delivering key concepts learned in our
academic career.
3
Performance Requirements
•
Functions and Capabilities
– Product must be accurate to depths of +/- 5 percent of actual depth
– Product must be able to measure depths up to 50 feet
– Product must read depth every 1 second
– Must be able to sense under the transducer within a 15 degree cone
– Must be able to work both with marine batteries and with D cell batteries
– Product must be able to differentiate small objects from the bottom of the lake
4
Performance Requirements
•
Modes of Operation
– The Product shall be able to turn on and off
•
Power Inputs
– The battery must be able to last for 5 hours on full operation without recharge
– The product must be able to operate on a standard 12 V marine battery
– The product must be able to operate on 8 standard D Cell batteries
•
Electrical Functions
– The product must be able to operate within a voltage range of 10-14.4V
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Operator I/O Inputs
– The On/Off switch must be a momentary on pushbutton switch
•
Mechanical Interfaces
– The product must be able to mount onto an L bracket
5
Standard Requirements
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Environment & Safety
– The product shall be able to operate in temperatures between 32 and 130
degrees Fahrenheit
– The product shall be able to operate in 0-90% non-condensing humidity
– The product shall be able to operate in altitude ranges from sea level to 8000
feet
– The product shall be able to be stored in temperature ranging from 20-150
degrees Fahrenheit
– The product shall be able to be stored in 0-90% non-condensing humidity
– The product shall be able to be stored in altitudes ranging from -500 to 60000
feet
– The product shall be able to be stored without operation for 10 years
6
System - Std Reqs: Market & Business
Case
Requirement
• Competitors
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Market Size
Average List Price
Market Geography
Market Demography
Intended Application
Material Cost
Manufacturing Cost
Annual Volume
Units to Specify
Humminbird, Lowrance,
Eagle, Garmin.
10M
$100
USA and Canada
14- up, Male and Female
Marine
$25
$35
10000 Units/yr
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Refined Block Diagram
Key
Power
Analog Signal
Ping Signal
Push Button #1
Push Button #2
LED Display
Backlight
Control
Ultrasonic
Transmitter
9V
Peter
Power Source
10 – 14.8 V
Joe
Ultrasonic
Receiver
5, 9 V
Isaac
CPLD
5V
Adam
User Interface
5V
Tony
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Refined Block Diagram Description Table
Block #
Block Name
Owner
Brief Description
Of Block Function
Power
Interfaces
Digital
Interfaces
Analog
Interfaces
1
Power Supply
Joe Reisinger
Converts 12VDC to 5VDC and
9VDC with minimal ripple
In: 12VDC
Out: 5VDC,
9VDC, 12VDC
None
Out: Vbat
2
CPLD
Adam Davis
CPU design using CPLD
Clock determined by required time
delay
In: 5VDC
Out: Display
In: Push
Buttons
In: Input from
Transducer
circuit
3
User Interface
Tony Johnson
Allows the user to interface with the
device, including display of depth
and push buttons for options
In: 5VDC
In: Display
Out: Push
Buttons
None
4
Transmitter
Peter Meyer
Transmits a signal into the water for
reflection detection for the receiver
In: 9VDC,
12VDC
None
Out: Signal
In: Signal from
CPLD
5
Receiver
Isaac Krull
Receives signals from the water
and sends the corresponding
signals to the CPLD
In: 5VDC,
9VDC
None
Out: Signal to
CPLD
9
Block Signal Table: Power
Power Signals
Power1 (Battery to Power Supply)
Power2(Supply to U/I-(LEDs))
Power3(Supply to Microprocessor)
Power3(Supply to Transformer)
Power4(Supply to Receiver)
Power5(Supply to Receiver)
Power6(Supply to Transmitter)
Type Direction
DC
DC
DC
DC
DC
DC
DC
Input
Input
Input
Input
Input
Input
Input
Block-Block Voltage Voltage Range Freq Freq Range % V-Reg V-Ripple
Interconnect Nominal
Min
Max Nominal Min Max
Max
Max
Connector Cable
12
10
14.8
N/A
N/A
N/A
15
1
PCB Trace
5
4.75
5.25
N/A
N/A
N/A
5
0.1
PCB Trace
5
4.75
5.25
N/A
N/A
N/A
5
0.1
Connector Cable
12
10.5
14.8
N/A
N/A
N/A
10
0.2
Connector Cable
5
4.75
5.25
N/A
N/A
N/A
5
0.1
Connector Cable
9
8.5
9.5
N/A
N/A
N/A
10
0.2
Connector Cable
9
8.5
9.5
N/A
N/A
N/A
5
0.1
10
Block Signal Table: Digital
Digital Signals
To - From
Block #'s
Type
Dir
Block-Block
Interconnect
Output
Structure
Input
Structure
Tech
Freq
Nominal
Logic
Voltage
Push Button #1
Push Button #2
Ping, Signal from Reciever Block
LED Display
LED Back Lit Display
Crystal
To Block 3
To Block 3
From Block 5
To Block 3
To Block 3
From Block 4
Digital
Digital
Digital
Digital
Power
Clock
Output
Output
Input
Output
Output
Input
PCB/Wire
PCB/Wire
Wire
PCB/Wire
PCB/Wire
PCB
Standard
Standard
N/A
Standard
Standard
N/A
N/A
N/A
Standard
N/A
N/A
Clock
TTL
TTL
Other
Other
Other
Clock
DC
DC
Variable
DC
DC
100 kHz
5V
5V
5V
5V
5V
Digital Signals
To - From
Block #'s
Type
Dir
Push Button #1
Push Button #2
Ping, Signal from Reciever Block
LED Display
LED Back Lit Display
Crystal
To Block 3
To Block 3
From Block 5
To Block 3
To Block 3
From Block 4
Digital
Digital
Digital
Digital
Power
Clock
Output
Output
Input
Output
Output
Input
Digital Signals
To - From
Block #'s
Type
Dir
To Block 3
To Block 3
From Block 5
To Block 3
To Block 3
From Block 4
Digital
Digital
Digital
Digital
Power
Clock
Push Button #1
Push Button #2
Ping, Signal from Reciever Block
LED Display
LED Back Lit Display
Crystal
Vih Min
Output
Output
Input
Output
Output
Input
N/A
N/A
3.9V
N/A
N/A
3.9V
Input Characteristics
Iih Max
ViL Max IiL Max
N/A
N/A
10mA
N/A
N/A
10uA
N/A
N/A
0.8V
N/A
N/A
0.8V
Output Characteristics
Voh Min
Ioh Max
VoL Max
3.9V
3.9V
N/A
9.0V
9.0V
N/A
10mA
N/A
N/A
100mA
100mA
N/A
N/A
0.8V
N/A
0.5V
0.5V
N/A
N/A
N/A
-10uA
N/A
N/A
-1uA
Vth Min Vth Max
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
IoL Max
N/A
-1.2mA
N/A
1uA
1uA
N/A
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Block Signal Table: Analog
To - From
Block #'s
2
2
Type
Direction
Analog
Analog
Output
Input
Block-Block
Interconnect
Ultrasonic Transducer
Ultrasonic Transducer
Coupling
Voltage Max
Amplitude
150 V
5V
Impedance
Min
Max
450
550
450
550
Freq Range
Min
Max
49 kHz 51 kHz
49 kHz 51 kHz
Leakage
Max
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Ethical/Societal Issues
•
Our depth finder is at risk of electrical faults and possible
electrocution if proper procedures to eliminate these risks are not
taken.
– Our unit will need to be enclosed in a waterproof enclosure.
– Proper safety grounds must also be implemented.
• These actions will greatly reduce the risk of possible electrical
faults or electrocution.
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The engineering of our sonar transmitter and receiver is the most
critical part of our product.
– If this isn’t functioning 100% correct, the product will be useless.
– To ensure this area of engineering is 100% correct numerous
extensive tests will be performed on the transmitter and receiver
components.
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Applicable Patents
Name: Portable Fish Finder
•
Patent Number: 6791902
Date: September 14, 2004
This patent could be designed around if we intended our unit to be
permanently used on a boat and not portable. A different mounting device other
than a suction cup could be used to mount the transducer to the boat.
Name: Method for determining depth values of a body of water
Patent Number: 5465622
Date: November 14, 1995
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This patent could be designed around by omitting the velocity sensor
used and assume the velocity of the sound signal to be relatively constant.
For averages lakes, the velocity will not vary greatly with the change in
depth. The depth our depth finder is designed for won’t be affected by
changing velocity due to depth.
Name: Depth Finder having variable measurement capabilities
Patent Number: 5065371
Date: November 11, 1991
•
This patent could be designed around by utilizing a different display than a
liquid crystal display. A typical CRT display or LED display could be used
instead. Also, our depth finder would be designed for use in fresh water
only.
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Burns from Hot, Touchable
Surfaces
• Mitigation Design/Devices/Materials/Packaging
– In the event of failure, the battery and power supply
shall be isolated from the user with some sort of
protective cover.
• Affected Blocks
– Power Supply
• Test(s) Required to Verify Protection
– Continuous use and thermal testing
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Unsafe Single Point/Device
Failures
• Mitigation Design/Devices/Materials/Packaging
– In case of device failure, an audible alarm will sound
– Materials shall be of non-corrosive, thermal treated material
• Affected Blocks
– User Interface, Transducer, CPLD
• Test(s) Required to Verify Protection
– Induce a failure during normal operation
– Conduct environmental testing on prototype materials
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Electric Shock
• Mitigation Design/Devices/Materials/Packaging
– The user interface will be isolated by using dielectric materials.
– Grounding and low potential at all conductive surfaces.
– Insulation of high voltages
• Affected Blocks
– User interface
– Power Supply
– Transducer Circuit
• Test(s) Required to Verify Protection
– Electrostatic Discharge Testing to 15kV
– Surface voltage potential sensing at all high voltage contained
components
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Abusive Or Unknowing Users
• Mitigation Design/Devices/Materials/Packaging
– Utilize warning labels on the device and user manual to not
allow children to use the device.
– Design a carrying case which is lockable to prevent unwanted
use by children.
– Allow the operation of push buttons at required time intervals
throughout the use of the CPLD/software
• Affected Blocks
– CPLD
• Test(s) Required to Verify Protection
– Random button pushing
18
Sharp Edges & Pinch Points
• Mitigation Design/Devices/Materials/Packaging
– All corners and edges will be rounded. Warning indications will
be documented in the user manual and near any trouble spots.
– The battery cable will consist of pinch proof connectors. Also,
the user interface will consist of push buttons rather than
switches.
• Affected Blocks
– User Interface, Power supply
• Test(s) Required to Verify Protection
– Physical inspection
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Magnetic Field Energy
• Mitigation Design/Devices/Materials/Packaging
– Twisted shielded cables
• Affected Blocks
– Transmitter and Receiver
• Test(s) Required to Verify Protection
– Magnetic Field Immunity
20
Electro-Static Discharge
• Mitigation Design/Devices/Materials/Packaging
– Electronic shielded enclosures
– Ground coupled user inputs
• Affected Blocks
– User Interface
• Test(s) Required to Verify Protection
– ESD Immunity Test
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RF Electric Field Energy
• Mitigation Design/Devices/Materials/Packaging
– RF shielded signal cables
• Affected Blocks
– Transmitter, Receiver, CPLD
• Test(s) Required to Verify Protection
– RF Conducted Immunity
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Interference with Other Electronic Systems
• Mitigation Design/Devices/Materials/Packaging
– Fuse to isolate power supply
• Affected Blocks
– Power Supply
• Test(s) Required to Verify Protection
– Power Surge Immunity Test
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The Depth Finder 600
Task
2007
Week 1
Week 2
Week 3
Week 4
Week 5
Week 6
Week 7
Week 8
Week 9
Week 10 Week 11 Week 12 Week 13 Week 14 Week 15
Planning
5-Sep
25-Sep
Product Design
18-Sep
Process Design/
Development
Product & Process
Validation
Feedback/
Assessment and
Corrective Action
18-Sep
31-Oct
27-Oct
31-Oct
21-Nov
21-Nov
5-Dec
Production
6-Dec
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Block Prototyping Plan Template
Block
Name
Block Area
(cm2)
Board #
Board
Comp
Board
Substrate Attachment Dimensions
(cm x cm)
Type
Type
Types of
Connectors
CPLD
2.413x1.5875
1
PCB
Through
Hole
9.652x6.35
Trace
U/I
4.826x3.175
1
PCB
Through
Hole
9.652x6.35
Trace
Power
Supply
3.413x1.5875
1
PCB
Through
Hole
9.652x6.35
Trace/Pad
Receiver
4.826x3.175
2
PCB
Through
Hole
9.652x6.35
Trace
Transmitter 4.826x3.715
2
PCB
Through
Hole
9.652x6.35
Trace
25
Block Description and Purpose Slide
Power Supply
•The power supply will consist of a battery pack containing 8 D-cell
batteries.
-It will contain a 5V regulator needed by the CPLD.
-A transformer will drive the transducer
•The purpose of this block is to supply all blocks with power necessary
to perform their functions.
-Powers the transducer and helps to provide a means of
portability.
26
Block Standard Requirements/Allocation
27
Block Performance
Requirements/Allocation
28
Block Signal Input/Output Summary
Power Supply
Block Name: Power Supply
Block Number: 1
Power Signals
To - From
Block #'s
Power1 VCC +5
Power2 VCC +9
Power3 VCC +12
2,3,4,5
4
1
Analog Signals
To - From
Block #'s
Analog 1
4
Type
DC Power
DC Power
DC Power
Type
Analog
Direction
Output
Output
Output
Direction
Input
Block-Block
Interconnect
Voltage
Nominal
PCB Trace
5.0V
Connector Cable 9.0V
PCB Trace
12V
Block-Block
Interconnect
Coupling
Connector Cable Direct
Voltage Range
Min
Max
4.75V
8.5
10.5
Voltage Max
Amplitude
150 V
5.25V
9.5
15.4
Freq
Nominal
DC
DC
DC
Impedance
Min
Max
800 ohm 1.2Kohm
Freq Range
Min
Max
N/A
N/A
N/A
Freq Range
Min
Max
49kHz 51kHz
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Block Diagram Breakdown
Power Supply
Transistor to
Power transducer
Marine Battery
5V Regulator
To Display, Microprocessor,
Transmitter/Receiver
Switch
+12V
To Transmitter/Receiver Circuit
D-Cell Battery Pack
9V Regulator
30
Block Preliminary Schematic
Power Supply
•+12V supply
•+9V, +5V regulated
•AC signal generated from
transmitter pulses
•Step-up transformer to
drive transducer
•Need to drive 150V bias
@ transducer after
transmitter pulses to
“listen” for return signal.
31
Block Preliminary Bill of
Materials
Power Supply
Part Number
Description
D- Cel l Bat t er i es
D- Cel l Bat t er y Pac k age
Lm7805- 5V Regul at or
Lm7805- 9V Regul at or
2 pi n MTA c onnec t or
4- pi n MTA c onnec t or
1uF c apac i t or c er ami c
10uF c apac i t or - c er ami c
Tr ans i s t or
Tr ans f or mer
3A f us e
1A f us e
Quantity
8
1. 000
1. 000
1. 000
2. 000
1. 000
4. 000
2. 000
1. 000
1. 000
1. 000
1. 000
32
Block Detailed Design Calculations &
Component Selection
•
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All components are to be thru-hole. This allows for easier prototyping.
Bypass capacitors are added to both sides of each regulator for decoupling.
The voltage regulators are of TO-220 package. They are cheap, heat sinkable
(in case too much current), and easily mountable
– 5V @ ~.750A = 3.75 W. Using a 5W regulator
– -9V @ .250A = 2.25W. Using a 5W regulator
•
Safety Devices: Fuses, especially for the transducer which has a high current
draw.
– Transducer ~2A in operation, +9 V supply ~250mA  3A fuse should suffice, maybe
higher
– +5 V supply <500mA from display, ~10mA from microprocessor, ~250mA to other
board so we are using a 1A fuse here.
•
Need to determine which transistor and transformer to use based on
calculations
– Switching speed of transistor
– Ratio of transformer ~15:1
• Needs to be driven @ 150VAC
– How to bias transducer @ 150VDC?
33
Transmitter
Block Description and Purpose
• The purpose of this block is to provide the signal to drive
the transducer
• Takes DC voltage and turns into 50 kHz square wave
• Square wave is amplified and then drives transducer
34
Block Diagram Breakdown Slide
From Power
LM555 Timer
Chip: 50 kHz
signal generator
From CPLD:
Control for how
Long signal is
generated
Amplification
Circuit
50 kHz Ultrasonic
Transducer
To CPLD
35
Block Preliminary Schematic
36
Important Equations
37
Performance Requirements
• Transducer must be in a water-tight enclosure
• Must receive at least 4.5 Volts from the power supply
• Transducer power supply must be able to generate 16
pulses at 50kHz, and shut off until the pulse is received
back.
• Amplifier must take approximately 6 V at 200mA, and
convert it to the transducer bias voltage of 150V
38
Preliminary Bill of Materials
•
•
•
•
•
National Semi-Conductor LM555 Timer Chip
RS 271-280 Micro-Size Potentiometer
RS 2N3904 Transistor
RS ¼ Watt, 5% Tolerance Resistors
.01uF Capacitors
39
Package Type Rationale
• LM555:
– Ability to create necessary frequency signal
– Ability to be shut off from outside source
– Stable operation between 4.5 and 16 Volts
– Running temperature range (0-70 degrees C)
– Low-Cost : $1.69 ind. cost
40
Package Type Rationale
• RS 271-280 Micro-Size Potentiometer
– Compact size
– Availability
– Easily tunable circuit
– Low-cost: $1.49
41
Package Type Rationale
• RS ¼ Watt, 5% Tolerance Resistors
– Power ratings meet needs: Typically can handle
between 200 and 250 Volts. They will not see more
than 150 V.
42
Receiver
• Purpose
– The receiver block will amplify an input signal from a
transducer.
– This amplified signal will than be fed into a tone
decoder which will swing low when the specified
signal is detected.
– This low will then go into a voltage comparator to give
the CPLD a clean signal.
43
Receiver Block Performance
Requirements
The receiver block must be able to amplify a signal from
+/-5 mV pk to 5 V pk for input into the tone decoder.
The output must produce a 0 V dc level +/- 100 mV
for input to the CPLD
Standard
Temperature range
Max current
Voltage rating
0-55 C
150 mA
4.5 – 5.5 V
44
Receiver Block Diagram
45
Receiver Schematic
46
Receiver Schematic
• A buffer will be placed before and after the
amplification block
• The variable resistor R2 will allow the circuit to be
tuned in on the desired frequency
• The LM311 will act as the voltage comparator
ensuring a dc logic low
• 150 mA fuses will be added on the 5V power and 9V
line to protect the Tone decoder and other ICs
47
Receiver Design Calculations &
Component Selection
•
•
•
•
•
Fo = 1 / (1.1 x (R2 +18k) x .001uF)
BW = 1070 x sqrt (vi / (fo x .02 uF)
+/- 5 kHz
Other capacitors on diagram are bypass caps
Resistor values were chosen for desired gain
48
Receiver Considerations
• There is a 30 ns fall time and 150 ns rise time
on output of decoder
• Fo will change +\- .1 % for every 1 degree
change in temperature.
• Bandwidth with change .05% for every 1
degree temperature change
49
Receiver Prototype Cost
•
•
•
•
•
•
•
7 resistors $.10
2 variable resistors $.75
LM741 $.84
LM311 $.55
LM567 $1.27
4 ceramic capacitors $.15
Total parts cost $4.91
• **** All parts are through hole
50
User Interface / Display
Purpose: Creates an interface with the CPLD to display
the depth being read. The display also has the
capability to switch the output of the CPLD between
English and metric.
The display is a 7 segment LED display with a common
anode. The common anode is connected to +5 volts.
The cathodes are connected to the CPLD along with a
current limiting resistor for each individual LED. The
CPLD grounds applicable signals to light up certain
LED’s corresponding to the correct depth reading.
51
Standard Requirements
Max Operating Temp Range:
Min Operating Voltage Range:
Maximum Current Draw:
0C to 55C
4.75V to 5.25V
500mA
Performance Requirements
Power Modes:
Display Type:
Display Char Matrix:
Display Size:
Switch Type:
On / Off / Error
7 Segment LED
3 Char./Row, 1 Row
1.9cm x 3.78cm
On / Off Pushbutton
52
Block Diagram of U/I
+ 5V
English/Metric
Pushbutton
On/Off
Pushbutton
CPLD
2 Wire Array
22 Wire Array
English/Metric
Backlight
LED Display
Resistor
Array
22 Wire Array
53
User Interface Schematic
•
•
•
•
Common Anodes connected to +5v
CPLD grounds cathode to illuminate LED’s
Current limiting resistors
Momentary on pushbuttons
54
User Interface Block – Bill of Materials
(1) - 7 Segment LED Display – LDT-A512RI
(26) - 280 ohm Resistor
(2) - LED
(2) - Normally open momentary on Push button
55
Calculations / Component Selection
Device Package Type:
LED Forward current:
LED Forward voltage:
Source Voltage:
Current Limiting resistor:
PCB Trace Width:
28-Dip 7 Segment LED
10mA
2.2V Typical
5V
(VS-VLED)/If = 280Ω (+/- 10%)
0.010” (0.3 A max)
56
CPLD – Definition
•
This block shall maintain the safety of the device as well as the primary
state control.
•
The block will control the transducer circuit as well as all the operator
interfaces.
•
The block will convert the time intervals from send to echo and produce a
numerical value of depth on the user interface.
•
This block will also control the power state of the product via a push
button input to the CPLD
57
CPLD – Standard Requirements
•
Must be comparable in cost to other manufacturers (Associated)
•
Must be able to send depth value to seven segment displays (Associated)
•
Must be able to withstand glitches from other blocks (Associated)
•
Design to minimize battery consumption (Allocated)
58
CPLD – Performance Requirements
•
Must be accurate to within 5% of total depth (Associated)
•
Must be capable of measuring depths up to 50 Feet (Associated)
•
Design to work with relatively noisy signals from transducer circuit
(Associated)
•
Design to incorporate error mode to ensure safe operation when not
retrieving a signal (Associated)
•
Be somewhat shock resistant for marine and portable use (Associated)
59
CPLD Block – Block Diagram
Output to 7-Segment Display
22 Sinking Outputs
22
Output to Meters/Feet LED’s
2 Sinking Outputs
2
From Power Supply
Power Input
Filtering
Power Supply to Processor
Input from Echo Receive
Circuit, 5V Logic Input
Main
Processor
CPLD
Input from User Interface
2 5V Logic Inputs
Clock
Output to Transducer Transmit Circuit
1 Sinking Output
60
CPLD – Schematic
61
CPLD – Bill of Materials
(1) - Lattice Semiconductor CPLD – M4A5 128/64
(3) - .1 uF Ceramic Capacitors
(1) - 100kHz Crystal Epson Toyocom SE3333-ND
62
CPLD – Bill of Materials
Detailed Design Calculations
- CPLD Selection
Requires clock speeds above 10kHz
Requires up to 32 input/Output pins
Requires minimum of 16 Registers
*Selection based on this material, Lattice Semiconductor M4A5 line best
suited for application while still remaining a low power device
-Crystal Selection
Requires 100kHz Speed
*Selection based on this material, operational temp within our specified limits
as well as being an energy saving device.
-Capacitor Selection
Requires .1 uF capacitance
*Selection based on this material, devices are easy to find and readily
available
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