Transcript Final Exam Review Powerpoint 12/1/2009

EE40
Final Exam Review
Prof. Nathan Cheung
12/01/2009
Practice with past exams
http://hkn.eecs.berkeley.edu/exam/list/?exam_course=EE%2040
EE40 Fall 2009
Slide 1
Prof. Cheung
Overview of Course
Circuit components:
R, C, L , sources
I-V characteristics
energy storage/dissipation
Circuit analysis:
Laws: Ohm’s, KVL, KCL
 Equivalent circuits (series/
parallel, Thevenin, Norton)
 Superposition for linear circuits
 Nodal analysis
 Mesh analysis
 Phasor I and V
First-order transient excitation/analysis:
Second Order RLC circuits
Bode Plots
EE40 Fall 2009
Slide 2
2
Prof. Cheung
Overview of Course
Logic gates;
Combinatorial logic (sum-of-products, Karnaugh maps),
sequential logic etc.
Semiconductors Devices
pn-diodes (many types)
FETs (n-channel, p-channel, CMOS)
Useful Diode and FET circuits:
Amplifiers: op-amp (negative feedback), rectifiers; wave
shaping circuits
EE40 Fall 2009
Slide 3
3
Prof. Cheung
Diode Circuit Analysis by Assumed Diode States
•1) Specify Ideal Diode Model or Piecewise-Linear
Diode Model
ID (A)
ID (A)
forward bias
forward bias
reverse bias
VD (V)
reverse bias
VDon
•2) Each diode can be ON or OFF
•3) Circuit containing n diodes will have 2n states
•4) The combination of states that works for ALL
diodes (consistent with KVL and KCL) will be the
solution
EE40 Fall 2009
Slide 4
Prof. Cheung
Example Problem: Perfect Rectifier Model
Sketch Vout versus Vin
Suggested problem: What if there is a 0.6V drop when diodes are on ?
EE40 Fall 2009
Slide 5
Prof. Cheung
Diode with Capacitor Circuit (e.g.Level Shifter)
VIN
-
VC
VIN
+
+
- VC +
C
t
VOUT
VIN(min)
VOUT
1
3
VOUT (t)= VC(t)+ VIN(t)
Finds out what happens to VC
when VIN changes
t
2
1) Diode =open, VC(t)=0, VOUT (t)= VIN(t)
2) Diode =short, VC(t)= -VIN(t) , VOUT(t)=0
,
3) Diode =open, VC(t)= -VIN(min), VOUT(t)= VIN(t)-VIN(min)
EE40 Fall 2009
Slide 6
Prof. Cheung
Example: Diode with RL Circuit
Sketch i(t)
Answer
Note: i(t) is
continuous
 = L/R = 0.05 msec
EE40 Fall 2009
Slide 7
Prof. Cheung
Load-Line Analysis
We have a circuit containing a two-terminal non-linear element
“NLE”, and some linear components.
First replace the entire linear part of the circuit by its Thevenin
equivalent.
Then define I and V at the NLE terminals (typically associated signs)
D
Nonlinear
9mA
element
250K 1M
+
-
1V
S
EE40 Fall 2009
Slide 8
N
L
E
D
ID
V+DS + 200K
2V
S-
Prof. Cheung
Example of Load-Line Analysis (con’t)
Given the graphical properties of two terminal non-linear circuit
(i.e. the graph of a two terminal device)
And have this connected to a linear
(Thévenin) circuit
D
N
L
E
Whose I-V can also be graphed
on the same axes (“load line”)
N
L
E
EE40 Fall 2009
V+DS + 200K
2V
S-
Application of KCL, KVL gives circuit solution
ID (mA)
D ID
10
The solution
!
200K
S
ID
+
-
2V
Slide 9
1
VDS (V)
2Prof. Cheung
Example : Voltage controlled Attenuator
VC and RC
Determines rd at
Q point of diode
EE40 Fall 2009
Slide 10
Prof. Cheung
Example : Voltage Controlled Attenuator
The large capacitors and DC bias source are effective shorts
for the ac signal in small-signal circuits
EE40 Fall 2009
Slide 11
Prof. Cheung
Three-Terminal Parametric Graphs
ID
3-Terminal
Device
G
VGS
+
-
ID (mA)
D
10
VGS = 3
VGS = 2
VGS = 1
S
Concept of 3-Terminal Parametric Graphs:
1
2
VDS (V)
We set a voltage (or current) at one set of
terminals (here we will apply a fixed VGS, IG=0)
and conceptually draw a box around the device
with only two terminals emerging so we can
again plot the two-terminal characteristic
(here ID versus VDS).
But we can do this for a variety of values of VGS
with the result that we get a family of curves.
EE40 Fall 2009
Slide 12
12
Prof. Cheung
Graphical Solutions for 3-Terminal Devices
ID
G
V
+
-
S
+
-
ID (mA)
D
200K
10
VGS = 3
2V
VGS = 2
VGS = 1
We can only find a solution for
one input (VGS) at a time:
First select VGS (e.g. 2V) and draw
ID vs VDS for the 3-Terminal device.
Now draw ID vs VDS for the 2V 200KW Thevenin source.
ID (mA)
1
10
The solution
!
The only point on the I vs V
plane which obeys KCL and
KVL is ID = 5mA at VDS = 1V.
1
EE40 Fall 2009
Slide 13
VDS (V)
2
2
13
VDS (V)
Prof. Cheung
SOLVING MOSFET CIRCUITS: STEPS
1) Guess the mode of operation for the transistor. (We will learn
how to make educated guesses).
2) Write the ID vs. VDS equation for this guess mode of operation.
3) Use KVL, KCL, etc. to come up with an equation relating ID and
VDS based on the surrounding linear circuit.
4) Solve these equations for ID and VDS.
5) Check to see if the values for ID and VDS are possible for the
mode you guessed for the transistor. If the values are possible for
the mode guessed, stop, problem solved. If the values are
impossible, go back to Step 1.
EE40 Fall 2009
Slide 14
Prof. Cheung
CHECKING THE ANSWERS
NMOS
Saturation
Cut-off
Triode
vGS •2) V < V – V in triode
DS
GS
T(N)
vDS  Vto
0 Vto
1) VGS > VT(N) in triode or saturation
VGS ≤ VT(N) in cutoff
VDS ≥ VGS – VT(N) in saturation
PMOS
Triode
Saturation
vDS  Vto
EE40 Fall 2009
Vto
Cut-off
0
vGS
1) VGS < VT(P) in triode or
saturation
VGS ≥ VT(P) in cutoff
2) VDS > VGS – VT(P) in triode
VDS ≤ VGS – VT(P) in saturation
Slide 15
Prof. Cheung
Example Problem : MOSFET Circuit
EE40 Fall 2009
Slide 16
Prof. Cheung
Example Problem : MOSFET Circuit
Find VGS such that VDS=2V
Answer
Guess Saturation Mode
Check:
VDS(=2V) > VGS-VT (=1.5-0.5=1V)
MOSFET indeed is in saturation mode
EE40 Fall 2009
Slide 17
Prof. Cheung
Example Problem : MOSFET Circuit
Find small-signal model parameters
=10-5 Siemens
EE40 Fall 2009
Slide 18
Prof. Cheung
How do you guess the right mode ?
Often, the key is the value of VGS.
(We can often find VGS directly without solving the whole circuit.)
ID
ID
VGS ≤ VT(N)
VGS = VT(N) + e
probably saturation
definitely cutoff
VDS
EE40 Fall 2009
VGS - VT(N) = e
Slide 19
VDS
Prof. Cheung
How do you guess the right mode ?
When VGS >> VTH(N), it’s harder to guess the mode.
ID triode mode
saturation mode
VGS - VTH(N)
If ID is small, probably triode mode
EE40 Fall 2009
Slide 20
VDS
Prof. Cheung
EXAMPLE
1) Since VGS > VTH(N), not in cutoff
mode. Guess saturation mode.
1.5 kW
2) Write transistor ID vs. VDS:
D
+
4V
_
ID
G
+
3V _
I D  I Dsa t  250  10 6 (3 V  1 V 
2
+
 1mA
VDS
_
3) Write ID vs. VDS equation using
KVL:
S
- VDS - 1.5 kW  ID  4V  0
GIVEN: VTH(N) = 1 V,
K= 250 m A/V2,
l = 0 V-1.
EE40 Fall 2009
Slide 21
Prof. Cheung
EXAMPLE
4) Solve VDS:
1.5 kW
ID = 1mA VDS = 2.5 V
D
+
4V
_
+
3V _
ID
G
5) Check:
+
VDS
_
ID and VDS are correct sign, and
VDS ≥ VGS-VT(N) as required in
saturation mode.
S
GIVEN: VTH(N) = 1 V,
½ W/L mnCOX = 250 m A/V2,
l = 0 V-1.
EE40 Fall 2009
Slide 22
Prof. Cheung
WHAT IF WE GUESSED THE MODE WRONG?
1) Since VGS > VTH(N), not in cutoff
mode. Guess triode mode.
1.5 kW
2) Write transistor ID vs. VDS:
D
+
4V
_
ID
G
+
3V _
ID = 2·250·10-6(3 – 1 – VDS/2)VDS
+
VDS
_
S
3) Write ID vs. VDS equation using
KVL:
- VDS - 1.5 kW  ID  4V  0
GIVEN: VTH(N) = 1 V,
K= 250 m A/V2,
l = 0 V-1.
EE40 Fall 2009
Slide 23
Prof. Cheung
WHAT IF WE GUESSED THE MODE WRONG?
4) Solve for VDS with quadratic
equation by combining 2) and 3):
1.5 kW
D
+
4V
_
ID
G
+
3V _
VDS = {4 V, 2.67 V}
+
VDS
_
5) Check:
VDS > VGS – VT(N) = 2V
Neither value valid in triode mode!
Guess is incorrect.
S
GIVEN: VTH(N) = 1 V,
K= 250 m A/V2,
l = 0 V-1.
EE40 Fall 2009
Slide 24
Prof. Cheung
Another Perspective
In this circuit, the transistor
delivered a constant current IDSAT
to the 1.5 kW resistor.
1.5 kW
This circuit acts like a constant
current source, as long as the
transistor remains in saturation
mode.
IDSAT does not depend on the
attached resistance if saturation
is maintained.
D
+
4V
_
+
3V _
EE40 Fall 2009
ID
G
+
VDS
_
IDSAT
1.5 kW
S
Slide 25
Prof. Cheung
Another Perspective
IDSAT does depend on VGS; one
can adjust the current supplied by
adjusting VGS.
RL
D
VDD
ID
+
_
VGS
EE40 Fall 2009
G
+
_
The circuit will go out of
saturation mode if
• VGS < VT(N)
or
• VDS < VGS – VT(N)
This can happen if VGS is too
large or too small, or if the load
resistance is too large.
+
VDS
_
IDSAT
RL
S
Slide 26
Prof. Cheung
ANOTHER EXAMPLE
D
1) What is VGS?
No current goes into/out gate.
VGS = 3 V by voltage division.
Guess saturation (randomly).
+
2) Write transistor ID vs. VDS:
1.5 kW
2 kW
ID
+
4V
_
G
6 kW
VDS
_
S
GIVEN: VTH(N) = 1 V,
K= 250 m A/V2,
l = 0 V-1.
I D  I Dsa t  250  10 6 (3 V  1 V 
2
 1mA
3) Write ID vs. VDS equation using
KVL:
- VDS - 1.5 kW  ID  4V  0
VDS=2.75V consisitent with saturation mode
Effectively the same circuit as previous example: only 1 voltage source in this case
EE40 Fall 2009
Slide 27
Prof. Cheung
The CMOS Inverter: Current Flow
N: sat
P: sat
VOUT
N: off
P: Triode
VDD
VDD
S
G
VOUT
I
A
D
G
C
N: sat
P: Triode
D
VIN
B
D
E
N: Triode
P: sat
S
N: Triode
P: off
0
VDD
0
EE40 Fall 2009
i
Slide 28
VIN
Prof. Cheung
Another CMOS Example: The LATCH
VDD
VDD
CLK
VIN
CLK
EE40 Fall 2009
Data (VIN) is written to the
internal node (VOUT_INT)
when the clock is low.
VOUT remains frozen.
CLK
VOUT_INT
VOUT
CLK
Slide 29
When the clock is high.
The (inverted) internal
node voltage is written to
VOUT. The internal node
VOUT_INT remains frozen
Prof. Cheung
THE LATCH
CLK
CLK
0V
VDD
VIN
When CLK is low the lefthand transistors conduct. The
right-hand transistors are open.
VDD
VDD
VOUT_INT
VOUT_INT is charged to VIN.
VOUT
VOUT remains the same; there is no
charging path.
CLK
CLK
VDD
0V
EE40 Fall 2009
Slide 30
Prof. Cheung
THE LATCH
CLK
CLK
VDD
0V
VIN
When CLK is high,
the right-hand transistors
conduct.
the left-hand transistors are
open.
VDD
VDD
VOUT_INT
VOUT
VOUT is changed to VOUT_INT.
CLK
CLK
0V
VDD
EE40 Fall 2009
VOUT_INT remains the same;
there is no charging path.
Slide 31
Prof. Cheung
CONCEPT OF STATE
CLK
VIN
CLK
EE40 Fall 2009
A latch stores a “1” or “0”.
VDD
VDD
CLK
Next
State
The stored value is known
as the “state”.
Current
State
This is one of the
basic elements needed
to make a “state
machine” (covered in
EE 20 and CS 61C).
CLK
Slide 32
Prof. Cheung
LATCH AS GATEKEEPER
A signal may have to go through a complex system of gates, with
paths of different delays: possibility of false output!
Combinatorial Logic
Signal propagates all the way through
Includes our logic gates: NAND, NOT, etc.
EE40 Fall 2009
Slide 33
Sequential Element
Prevents changes in
output until signaled
Prof. Cheung
Amplifier Efficiency
Power Supply A
Load
Source
Amplifier
Power Supply B
Amplifier Efficiency 
= 8/22.5 =36%
EE40 Fall 2009
Slide 34
Source
Pi = (10-3V)2/105W
=10-11 W
Load
P0 = (8V)2/8W
=8 W
Power Supplies
Ps = 15W+7.5W
= 22.5 W
Amplifier
Pd = 22.5W+10-11W-8W
= 14.5 W
Prof. Cheung
Differential Signal and Common Mode Signal
Redefine the inputs in terms of two other voltages:
1. differential mode input vid  vi1 – vi2
2. common mode input vicm  (vi1 + vi2)/2
so that
vi1 = vicm + (vid/2) and vi2 = vicm - (vid/2)
v o  Ad v id  Acm v icm
“differential
mode gain”
EE40 Fall 2009
“common
mode gain”
Slide 35
Prof. Cheung
Common Mode Rejection Ratio
Ad
CMRR (in dB )  20 log
Acm
Example
•Differential signal from sensor = 1mV (peak).
We want outputs signal > 1V implies Ad> 1000
•Common mode signal =100V (from power line).
We want common mode signal < 0.1V implies
Acm <10-4
Therefore CMRR needs to be > 20log(107)= 140dB
EE40 Fall 2009
Slide 36
Prof. Cheung
Offset Voltage, Offset Current, and Bias Current
Given
Voff=2mV
IB= 100nA
Ioff= 20nA
Acm=1
Ad=100
Both input
terminals to ground
through 100kW
resistors
Use superposition
Vo = Ad(Vvoff+VIoff)+ Acmvicm= 100(0.001667+0.001667)+1(0.01)=0.3343V
EE40 Fall 2009
Slide 37
Prof. Cheung