Can analog and digital applications tolerate the intrinsic noise of
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Transcript Can analog and digital applications tolerate the intrinsic noise of
Can analog and digital applications tolerate the
intrinsic noise for aggressively scaled field-effect
transistors?
G.Albareda, D.Jimenez and X.Oriols
Universitat Autònoma de Barcelona - Spain
E.mail: [email protected]
UPoN
2008 June 2-6, 2008
Lyon,Lyon
FRANCE
G. Albareda
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Outline
I.- Introduction: 3D, 2D and 1D ballistic nanoscale FETs
I.1.- Intrinsic noise in ballistic nanoscaleFETs
I.2.- Analytical Signal-to-noise ratio (S/N)
I.3.- Analytical Bit-error ratio (BER)
II.- Monte Carlo simulation of 3D, 2D and 1D FETs
II.1.- Simulator description
II.2.- Numerical results
III.- Conclusions
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I.1.- Intrinsic noise in ballistic 3D, 2D and 1D FETs
The size of the transistors shrinks for
faster and smaller microchips
Ly
Lx
Lz
1,2,3,4 gates to improve gate control (Lx>Ly,Lz)
x
z
y
Ly
Lz
B
B
3D Bulk FET
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When Ly and Lz become comparable to
the electron de Broglie wavelength, the wavenature of the electron is manifested.
Ly B
Lz B
2D Quantum Well FET
Ly
Lz
B
B
1D Quantum-Wire FET
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I.1.- Intrinsic noise in ballistic 3D, 2D and 1D FETs
OUR GOAL
Study the noise performance of these aggressively scaled
FET in analog and digital circuit applications
I(t)
We only consider the “intrinsic” sources of noise due to
electron-electron interactions (intrinsic field-effect)
.- Exclusion (Pauli) interaction in the contacts
.- The Coulomb interaction in the active region
We consider ballistic (“ideal”) FETs:
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No phonon scattering
No surface roughness
No impurity scattering
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I.2.- Signal to noise ratio (S/N)
Analog FET amplifier
VD>VDS
3D 30 x 10 x 8 nm3
6
VG>VGS
RL
Current ()
5
4
3
2
1
0
0,0
0,2
0,4
0,6
0,8
Drain Voltage (V)
1,0
1,2
Sub-thresohold region
G0
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I.2.- Signal to noise ratio (S/N)
IDS(t)
Analog FET amplifier
D
IDS(t)
NS IDS(t)
G
S
IDS(t)
RLL
In the saturation region G0:
I DS t I DS t GVDS
Using the superposition principle:
For2 RD RL
N RL
RD RL
2qI DS F B
RD RL
S2 RL
S RL
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SI 0
F
2e I DS
I DS 1 2
VCC
RD RL
2 VCC
I
2
I
F
DS
DS
2 2
N
qB
R
R
R
R
R
D LL
D
D
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I.2.- Signal to noise ratio (S/N)
The role of electron confinement
on the average and noise current
S RL
N RL
Ly
Lx
Lz
I 1
DS
2qB F
S RL
N RL
I DS2 1
S 0 B
I f (E )
S (0) f ( E)·1 f ( E)
Eq
Ec _ max
S
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Ef
S/N3D > S/N1D
D
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I.3.- Bit error ratio (BER) in digital applications
Digital FET inverter:
VCC
Bit error ratio (BER):
VCC
C
OFF
ON
P
P
‘0’
‘1’
ON
N
noisy
Vth
Vo
noisless
V
‘1’
Vi
OFF
N
0
1
VD>VDS
6
VG>VGS
Current ()
5
D
4
3
IDS(t)
G
NS
IDS(t)
IDS(t) 0
2
S
1
0
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0,0
0,2
0,4
0,6
0,8
Drain Voltage (V)
1,0
1,2
Sub-thresohold region
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I.3.- Bit error ratio (BER) in digital applications
VCC
VCC
OFF
ON
P
P
‘0’
‘1’
noisless
Voltage fluctuations:
VDS I
‘1’
IDC
ON
N
Thermal noise: SI (0) SS (0) SD (0) 4·kB ·T·G
OFF
N
noisy
Noise Power:
NV 0
1
1
C 1
j
RT C
1 4 k BT
tan 1 2 f c RT C
C
Bit error ratio (BER):
Vo
D
IDS(t)
G
NS
IDS(t)
Vth
V
C
S
0 A/2
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C3D > C1D
BER3D < BER1D
1
Vi
[ref] L.B.Kish, Physics Letters A 305 (2002) 144-149.
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Outline
I.- Introduction: 3D, 2D and 1D nanoscale FETs
II.- Monte Carlo simulation of 3D, 2D and 1D FETs
II.1.- Simulator description:
II.1.1.- Confined particles in 1D FETs
II.1.2.- Exact 3D Coulomb interaction
II.1.3.- Electron injection model with “Pauli” correlations
and charge neutrality
II.2.- Numerical results:
II.2.1.- Average current
II.2.2.- Signal to noise ratio
II.2.3.- Bit error ratio
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III.- Conclusions
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II.1.1.- Confined particles in 1D FETs
Silicon (100) channel orientation
1-D
Ly
Lx
Lz
vy 0
Guess:
vz 0
Lx=15 nm Ly=5 nm
Lz=2 nm
y
No electron
confinement
2 k x2
E
E1qD
2·mt
z
E1qD 0.1eV 0.08 eV
Quantum potential for the x system
E1qD 0 x Lx
Qx y ( x, y(t ), z (t ), t )
0 elsewhere
E
y
E1qD
x
This guess is quite accurate when there is only one relevant quantized energy
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[ref] X.Oriols, Physical Review Letters, 98, 066803 (2007)
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II.1.2.- Exact 3D Coulomb interaction
3D Coulomb interaction beyond the mean-field approximation
•• Exact
term
Mean-field
NOT
SEPARABLE
SEPARABLE
22
2 22 2 1
q
1
q
HHexact
UUkextkextrkrk
k " k2m* 2mk* k 2 k2 k jj4 4 rr
"mean
field
kk
00 kjkj
k j
Long-range
Long-range + Short-range
ERROR
Long-range
+
Short-range
Longrange
# e- per cell > 1
mean-field (1 Poisson Eq.)
exact-field (N Poisson Eqs.)
# e- per cell = 0 or 1
1nm-5nm
DX
[ref] G.Albareda et al, J. Comp. Electr. (2008)
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II.1.3.- Electron Injection model with “Pauli” correlation and
charge neutrality
Pauli correlation
Time-dependent version of Landauer-Buttiker boundary conditions
f (E)
Temperature ; T>0
I(t)
e
e
to
0
1
1 exp ( E E f ) /( k B T )
e
t
Binomial injection process
t0 ( y , z , k x , k y , k z )
#D
t
n#D
[ref] X.Oriols et al. Solid State Electronics, 51, 306 (2007)
[ref] T.Gonzalez, Semicond. Sci. Technol. 14, L37 (1999)
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II.1.3.- Electron Injection model with “Pauli” correlation and
charge neutrality
Charge neutrality
Our injection model, coupled to the boundary conditions of the Poisson
equation, does also assures charge neutrality at the contacts
Continuity equation
J 0
t
For a good conductor
J t, r E t , r
Local Gauss equation
t, r
E t , r
Practical Monte Carlo implementation
At each time step:
d r, t
r, t 0
dt
=/
t
EC N D x n t , x
[ref] H.Lopez, G.Albareda et al., J. Comp. Electr. (2008)
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II.2.1.- Average current
Average current
No scaling rule: SiO2 oxide thickness: tox=2 nm
Contact doping: 2·1019cm-3
Vgate
Vdrain
‘0’0V
‘1’0.5V
Vgate
VD>VDS
36
33
30
27
24
21
18
15
12
9
6
3
0
3D 30 x 10 x 8 nm3
VG>VGS
6
=0.5V
1D 15 x 5 x 2 nm3
VG>VGS=0.35V
5
Current ()
Current ()
VD>VDS
4
3
2
1
0,0
0,2
0,4
0,6
0,8
Drain Voltage (V)
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1,0
1,2
Sub-thresohold region
0
0,0
0,2
0,4
0,6
0,8
Drain Voltage (V)
1,0
1,2
Sub-thresohold region
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II.2.2.- Signal-to-noise ratio
S/N comparison
1.0
30
6
10
1D
3D
-0,1
0,0
0,1
0,2
Drain Current ()
7
10
3D
1D
25
20
0.8
15
0.7
10
0.6
5
-0.1
Vdrain=0.5 V
Vgate
Vgate
0.1
0.2
0.5
3D Average current > 1D Average current
3D Fano Factor < 1D Fano Factor
S/N
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0.0
Gate Voltage (V)
Gate Voltage (V)
Amplifying configuration (saturation region)
0.9
Fano Factor
Signal-to-Noise ratio S/N
8
10
1 I
2·q·B F
B 1 MHz
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II.2.3.- Bit-error-degradation
BER error probability
Efd
Vgate=0.5 V
1
1
0
ECd
Efs
5ns simulations (time step=2·10-16)
ECs
Vgate=0.5 V
0,3
VDS
Q
C
Drain Voltage (V)
0,2
0,1
0,0
-0,1
-0,2
-0,3
2
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3
Time (ps)
4
5
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II.2.3.- Bit-error-degradation
BER error probability
1
3D
5THz
1THz
C=5·10-18F
dP/dV
dP/dV
dP/dV
1
1
10 0
0
10-1
-1
10
-2
10
-3
10
-4
10 -5
10
10-6
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
10
-0,4
500GHz 50GHz
-0,2
0,0
0,2
0,4
0,4
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-13
10
1D
5THz
1THz
C=1·10-18F
-0,4
Drain Voltage (V)
500GHz
50GHz
-0,2
0,0
0,2
0,2
0,4
0,4
Drain Voltage (V)
According to our Vgate=0.5
analitycal
V estimation, smaller FETs (capacitors) are noisier.
Our 3D FETs can hold
frequencies up to 500GHz
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Our 1D FETs can’t hold
frequencies
0.5 V ; of
V 500GHz
0.0 V
Von
off
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III.- Conclusions
We have developed an accurate Monte Carlo simulator for 3D, 2D and 1D
nanoscale FET.
For analog applications, smaller devices produce a minor average current and a
larger Fano factor, leading to a signal-to-noise (S/N) degradation.
For digital applications, smaller devices are more sensible to electrostatics (i.e.
smaller capacitance), and provide a degradation of the Bit Error Ratio (BER).
In summary, Smaller FETs are noiser for either analog or digital applications.
Merci beaucoup
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