Transcript LiaisonReportNASiliconWafer20110824

NA Silicon Wafer Committee Liaison
Report
Updated August 24, 2011
Meeting Information
• Last meeting
– Wednesday, July 13, 2011, SEMICON West
• San Francisco Marriott Marquis, CA
• Next meeting
– Tuesday, October 25, 2011, NA Fall Standards
Meeting
• Intel in Santa Clara, CA
• www.semi.org/standards for the latest update
New SNARFs
• 5251: Revision of SEMI M1 Specifications for Polished Single
Crystal Silicon Wafers (Re: node-specific guide )
• 5252: Revision of SEMI M57 Guide for Specifying Silicon
Annealed Wafers” with Title Change from Guide to
Specification
• 5253: Revision of SEMI M49 Guide For Specifying Geometry
Measurement Systems For Silicon Wafers For The 130 nm To
22 nm Technology Generations (Re: Updating Parameters for
Next Wafer Generation)
NA Silicon Wafer Committee
Committee Chairmen
Dinesh Gupta /STA
Noel Poduje /SMS
Silicon Wafer Committee
C: Dinesh Gupta - STA
C: Noel Poduje - SMS
TE: Murray Bullis –
Materials & Metrology
Specifications
Metrology
Int’l Annealed Wafers TF
Dinesh Gupta -STA
Int’l 450 mm Wafer TF
Mike Goldstein - Intel
Int’l Advanced Wafer
Geometry TF
Noel Poduje – SMS
Jaydeep Sinha – KLATencor
Int’l Epitaxial Wafers TF
Dinesh Gupta - STA
Int’l Polished Wafers TF
Murray Bullis Materials & Metrology
Int’l Advanced Surface
Inspection TF
John Stover - TSW
George Kren - KLA-Tencor
Int’l SOI Wafers TF
George Celler - SOITEC
Committee
Int’l Test Methods TF
Dinesh Gupta - STA
Int’l Terminology TF
Murray Bullis Materials & Metrology
Ballots passed review at West Meeting [1]
– Document 5035A - Line Item Revision to M62-0309, Specifications
for Silicon Epitaxial Wafers
– Document 5043A - Revision of SEMI MF1048-1109, Test Method for
Measuring Reflective Total Integrated Scatter
– Document 5090 - Revision of SEMI M1-0611, Specifications for
Polished Single Crystal Silicon Wafers
– Document 5166 - Revision of SEMI M57-0704, Guide for Specifying
Silicon Annealed Wafers
– Document 5167 - Line Item Revision to SEMI M49-0311, Guide for
Specifying Geometry Measurement Systems for Silicon Wafers for the
130-nm to 22-nm Technology Generations
Ballots passed review at West Meeting [2]
–
–
–
–
–
Document 5161 - Reapproval of SEMI MF1763-0706, Test Methods for
Measuring Contrast of a Linear Polarizer
Document 5162 - Reapproval of SEMI MF397-1106, Test Method for
Resistivity of Silicon Bars Using a Two-Point Probe
Document 5163 - Reapproval of SEMI MF576-0706, Test Method for
Measurement of Insulator Thickness and Refractive Index on Silicon
Substrates by Ellipsometry
Document 5164 - Reapproval of SEMI MF728-1106, Practice for Preparing
an Optical Microscope for Dimensional Measurements
Document 5165 - Reapproval of SEMI MF978-1106, Test Method for
Characterizing Semiconductor Deep Levels by Transient Capacitance
Techniques
Ballots Failed review at West Meeting
• Doc. 5070 - Revision of SEMI M76-0710,
Specification for Developmental 450 mm Diameter
Polished Single Crystal Silicon Wafers Document
Ballots approved for cycle 5 and 6-2011 [1]
• Doc. 5034, Revision of SEMI M71-0310 Specification for
Silicon-on-Insulator (SOI) Wafers for CMOS LSI
• Doc. 5253, Revision of SEMI M49 Guide for Specifying
Geometry Measurement Systems For Silicon Wafers for The
130 nm To 22 nm Technology Generations
• Doc. 4766, Revision to SEMI M52-0307 Guide for Specifying
Scanning Surface Inspection Systems for Silicon Wafers for
the 130 nm, 90 nm, 65 nm, and 45 nm Technology
Generations
Metrology Group
• Int’l Advanced Wafer Geometry TF/Noel Poduje
(SMS)
– New NA Co-leader: Jaydeep Sinha (KLA-Tencor)
– Doc. 5167, Line Item Revision to SEMI M49-0311,
Guide for Specifying Geometry Measurement Systems
for Silicon Wafers for the 130-nm to 22-nm
Technology Generations
• Correcting the negative value of ZDD
• Ballot was approved at SEMICON West
– Drafting doc. 4812, New Standard: Guide for Flatness
Measurement on 450 mm Wafer
Metrology Group
• Int’l Advanced Wafer Geometry TF/Noel Poduje
(SMS) [2]
– Drafting doc. 5091, Revision of SEMI M49-0311, Guide for Specifying
Geometry Measurement Systems for Silicon Wafers for the 130 nm to
22 nm Technology Generations (Re: ZDD parameter)
– Drafting doc. 5251, Revision of SEMI M1 Specifications for Polished
Single Crystal Silicon Wafers (Re: node-specific parameters guide)
• Work is to be done under Polished Wafer TF
– Technical presentations from ASML, Intel, KLA-Tencor on wafer
geometry
• See presentation in SEMICON West committee minutes
attachments
Metrology Group
• Int’l Advanced Surface Inspection
TF/John Stover (TSW)
– Drafting doc 4766 Revision to M52-0307 Guide for
Specifying SSIS for Si. Wafers for the 130 nm down to
11 nm Technology Generations
• Down to advanced 11 nm technology node
• Ballot was submitted in cycle 5-11, to be reviewed at
Europa
– Doc. 5043A, Revision to MF1048-1109 Test Method for
Measuring the Reflective Total Integrated Scatter,
• The rewrite was necessary because of errors found in the
existing document
• Ballot was approved at West, pending ISC Audit and Review
Specifications Group
• Int’l 450 mm Wafer TF/Mike Goldstein (Intel)
– Drafting doc. 5070, Revision to SEMI M76-0710, Specification
for Developmental 450 mm Diameter Polished Single Crystal
Silicon Wafers (Re: Edge Shape Design)
• Ballot failed at SEMICON West, sent back to TF for further
rework and reballot
– Drafting doc. 5071, Revision to M76, Specification for
developmental 450 mm diameter polished single crystal silicon
wafers
• (Re: wafer back surface contamination and defectivity
requirements.)
– Drafting doc. 5112, New Standard: 450 mm Diameter Polished
Single Crystal Silicon Wafers (Re: for 32 nm IC Manufacturing
Node)
Specifications Group
• Int’l SOI Wafer TF/George Celler
(SOITEC)
• Draft doc. 5034 Revision of SEMI M71-0310 Specification for
Silicon-on-Insulator (SOI) Wafers for CMOS LSI
– Extension of the SOI film thickness from the current 20 nm
minimum to a new minimum of 10 nm or even a lower limit.
– Ballot to be submitted in cycle 6-2011 for review at
SEMICON Japan in December 2011
• Si Photonics has some unique SOI requirements that would
require a separate standard. SOI for power devices is another
distinct area
Specifications Group
•
Int’l Epitaxial Wafer TF/Dinesh Gupta
(STA)
– Doc. 5035A Revision to SEMI M62-0309 Specifications for Silicon Epitaxial Wafers
•
•
Addition of 22 nm epi guide
Ballot was approved at SEMICON West, pending ISC
Procedural review
– Discussed 450 mm epi wafer for future
business
Specifications Group
•
Int’l Annealed Wafer TF/Dinesh Gupta
(STA)
– Drafting doc. 5166, Revision of SEMI M57-0704
Guide for Specifying Silicon Annealed Wafers
•
–
Ballot was approved at SEMICON West, pending ISC
Procedural review
New SNARF submitted: Doc. 5252 Revision of SEMI
M57 Guide for Specifying Silicon Annealed Wafers” with
Title Change from Guide to Specification
Specifications Group
•
Int’l Polished Wafer TF/Murray Bullis
(Materials & Metrology)
– Doc. 5090, Revision of SEMI M1-0611,
Specifications for Polished Single Crystal Silicon
Wafers (Re: Addition of 450 mm polished wafer)
•
Ballot was approved at SEMICON West, pending ISC
Procedural review
– Discussed Template method for verifying the
acceptability of parameter-based edge profile
specifications be removed from M76 (and M1)
Committee TF
• Int’l Terminology TF/Murray Bullis
(Materials & Metrology)
– Revision SEMI M59-0211, Terminology for Silicon
Technology
• Ongoing revision
• Future works include polysilicon, wafer packaging,
microscopy and optics terms
Committee TF
• Int’l Test Methods TF/Dinesh Gupta (STA) [1]
– 5 Year Reapproval Ballots passed at SEMICON West 2011
•
•
•
•
•
–
Document 5161 - Reapproval of SEMI MF1763-0706, Test Methods for Measuring Contrast
of a Linear Polarizer
Document 5162 - Reapproval of SEMI MF397-1106, Test Method for Resistivity of Silicon
Bars Using a Two-Point Probe
Document 5163 - Reapproval of SEMI MF576-0706, Test Method for Measurement of
Insulator Thickness and Refractive Index on Silicon Substrates by Ellipsometry
Document 5164 - Reapproval of SEMI MF728-1106, Practice for Preparing an Optical
Microscope for Dimensional Measurements
Document 5165 - Reapproval of SEMI MF978-1106, Test Method for Characterizing
Semiconductor Deep Levels by Transient Capacitance Techniques
Continue to look into remaining 5 year reapproval standards
Standard Technical Education Programs
(STEP) from SEMICON West
• Wafer Edge Profile for 450 mm
– In many advanced wafer applications, a much tighter specification of
the edge profile is required to control variations in subsequent circuit
processing. These specifications frequently include values for certain
characteristics that describe the segments of the edge profile contour.
The relevant parameters used for characterizing the edge profile in
more detail than in the past will be discussed in the program as well as
the methods used for extracting them from measured edge profiles.
These new parameters require a new format for specifying (the edge
profile of) wafers, which will also be presented.
• Approx. 20 people attended
• Presentations from Siltronic, KoCos, KLA-Tencor, Intel
• Proceedings can be found at
– http://www.semiconwest.org/node/6621
Contact
• For more information, please contact Kevin
Nguyen at [email protected]