Transcript 48x36 Poster Template

New Graphene-based Logic Gates with
Lower Power Consumption
Kaisar Kussinov and Ainur Rakhymbay
Objectives
2. Methodology
To propose new design of logic gates to overcome physical
limitations of silicon based logic gates and reduction of total
energy for logic gates with feature size of less than 100nm.
1. Introduction
Graphene is most promising materials, which has unique
electrical, optical and thermal properties. As graphene has
high electrical and thermal conductivities, electrons in its
structure move with very small resistance wherein with lower
power release. Therefore, graphene is more attractive
substitute for silicon [1]. Despite of all these advantages,
there is absence of the energy gap between conduction and
valence bands. Several solutions were offered to this
problem, but most adopted is the patterning graphene sheets
into narrow stripes called graphene nanoribbons (GNRs) [2].
As a result GNRs creates small energy gaps which is capable
for implementation of FETs.
3. Results
The length and width of proposed design are L=16 nm and
W= 46 nm respectively. The channel width WCH is defined
through the number of dimers N in the GNR lattice as (1),
where dcc is the carbon to carbon distance and equals to
0.142 nm. Then the gate width of GNR is computed as (2),
where 2WSP is the spacing between ribbons.
Table1. Parameter values for graphene
Figure2. Four ribbon GNRFET
WCH =1.73* dcc (N+1)/2
Parameter
L
W
Tox
2*WSP
nRib
N
KP
CGDO
CGSO
WG = (2Wsp+WCH )*nRib
Value
16 nm
46nm
1n
2.5 nm
4
12
18.95e-15 F/um
2.25e-15 F
2.25e-15 F
(2)
VSC=VL+VP = (-Qt)/Ce
2. Advantages
•
•
•
•
•
•
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Fast (100 times faster than MOSFET)
Light
Sturdy
High mobility (200,000cm2/Vs)
Less heat dissipation
High current-carrying capacity
High thermal conductivity
Excellent switching properties
TEMPLATE DESIGN © 2008
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Qt=CsVs + CgVg + CdVd + Csub Vsub
(3)
Ce = Cs + Cg + Cd + Csub
The parasitic capacitances were considered during the
device simulation. They were calculated by using equation
(4).
C (gs-val) = 1.26*10-10 WG (0.8-0.2*Tox+0.015*T2ox) (4)
CGDO=CGSO=nRib*C (gs-val)
Figure3. IV characteristic for n-type MOSFET
(1)
The channel surface potential VCS of GFET was obtained
by using equation (3), where Qt is the total sum of
capacitance at all the four terminals and Ce is the total
charge.
Figure1. 3D model of GNRFET
Figure 3 and Figure 4 illustrate the IV characteristics of n
type MOSFET and GNRFET respectively. These simulations
were conducted in TannerEDA tools. Comparing these
figures it can be concluded that linear conductance of the
GNRFET is lower than of the MOSFET. Additionally,
GNRFET reaches higher saturation values than MOSFET.
Figure4. IV characteristic of n-type GNRFET
TABLE 2. Propagation delay and average power consumption of GNRFET and MOSFET
Logic
Gates
Inverter
Two-input
NAND
Propagation delay,
tp (ps)
GNRFE MOSFE
T
T
4.825
14.020
Average Power, Pav
(nJ/s)
MOSFE
GNRFET T
2.900
96.11
7.059
3.130
44.90
124.04
8. Conclusion
In this project GNRFET and Si-CMOS characteristics were
discussed and compared interms of delay and average power.
Based on the results it can be concluded that GNRFET is better
than Si-CMOS for low power applications because GNRFET has
lower average power and time delay than MOSFET.
Reference list
S. Miryala, A. Calimera, E. Macii and M. Poncino, “Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates”, IEEE Digital System Design
(DSD), pp. 365-371, 27-29 August 2014
V. Tenace, A. Calimera, E. Macii, M. Poncino, “Pass-XNOR logic: A new logic style for P-N junction based graphene circuits,” Design, Automation and Test
in Europe Conference and Exhibition (DATE), 2014 , pp. 1-4, 24-28 March 2014
Y-Y. Chen, A. Rogachev, A. Sangai, G. Iannaccone, G. Fiori, and D. Chen (2013). A SPICE-Compatible Model of Graphene Nano-Ribbon Field-Effect
Transistors Enabling Circuit-Level Delay and Power Analysis Under Process Variation. IEEE/ACM Design, Automation & Test in Europe, pp. 1789-1794.
P. Michetti and G. Iannaccone, “Analytical Model of One-Dimensional Carbon-Based Schottky-Barrier Transistors”, IEEE Transactions Vol.57(7), July 2010