Transcript E-Beam - Web.UVic.ca - University of Victoria

Developing a Versatile Platform for Nanoscale Materials Characterization
Julia Bobak, Daniel Collins, Fatemeh Soltani, David W. Steuerman
Department of Chemistry, University of Victoria, 2010
Introduction
Device Fabrication
An optical mask was designed using Raith software,
written by electron beam lithography and etched
out of a chromium-coated glass substrate.
Graphene is a single layer of sp2-hybridized carbon atoms packed into a honeycomb
crystal lattice. It exhibits high crystal and electronic quality making it an exciting new
material for future electronics. In its pure form, it conducts electrons faster at room
temperature than any other known substance. As a result, research is currently being
conducted towards the use of graphene in a variety of applications such as supertough composites, smart displays, ultra-fast transistors and quantum-dot computers.
In order to further characterize the electronic properties of this novel material, a
reliable platform for the fabrication of graphene devices is crucial.
The mask was then used for optical lithography in
order to generate the desired pattern in gold on a
thermally oxidized silicon substrate.
Graphene was deposited on the pre-patterned
substrate by micro-mechanical cleavage.
7.5 mm
graphene
Lithography
Glass
PMMA
PMMA
Glass
Glass
spin coating
exposure
Glass
PMMA
PMMA
Glass
Glass
washing
etching
AZ5214
Si
UV
exposure
20nm Ti
developing
AZ5214
AZ5214
Si
Si
etching
0.8
FWHM: 40.8 cm-1
Peak: 2646.8 cm-1
FWHM: 72.1 cm-1
Peak: 2666.7 cm-1
FWHM: 50.4 cm-1
Peak: 2685.5 cm-1
0.6
0.4
0.2
10 μm
0.0
50nm Au
Si
Mask
Si
Si
spin coating
AZ5214
1.0
2500 2550 2600 2650 2700 2750 2800 2850 2550
2900 2600
2550 2600 2650 2700 2750 2800 2850
Wavenumber (cm-1)
Monolayer Graphene
2650 2700 2750 2800 2850
-1
-
Wavenumber (cm )
Bilayer Graphene
Conclusions
Graphite
deposition
E-Beam and Optical Lithography
E-Beam
• Feature size primarily dependent on the size of the
beam of electrons – nanoscale structures (~50 nm)
• Low throughput – each spot on a feature is exposed to
the beam one-at-a-time in series
• Pattern written directly using the beam of electrons
• Can be extremely expensive
Electrical Characterization
1.6
Transport measurements are conducted by applying
Source
Drain
a voltage (V) through the “Source” electrode and
A
V
measuring the resultant current (I) through the
Graphene
“Drain” electrode. If a plot of current versus voltage
300 nm thermal SiO2
(termed an I-V curve) is linear then the material
(100) Si-Boron doped
obeys Ohm’s Law:
P+ 0.001-0.005 ohm-cm
V = IR
Optical
• Feature size limited by the wavelength of UV light –
used for microscale structures
• High throughput – all features are defined in parallel
• Requires an optical mask to generate the pattern
• Relatively inexpensive and rapid
I-V Curve of
Graphene Device
where R is the resistance of the material.
V
Gate
A field effect transistor (FET) relies on an applied
field to alter the conductivity of (to dope) a semiconductor, in this case graphene. This is achieved by
applying a second voltage (the gate voltage) to the
backside of the substrate.
1.4
1.2
1.0
Current (A)
300nm SiO2
developing
Normalized Intensity (counts)
100nm Cr
Electron beam lithography was used a second time to write
small wires connecting the graphene samples to the contact
pads. Characterization was then carried out using scanning
electron microscopy (SEM) and transport measurements.
Raman spectroscopy was used to identify the most promising single layer graphene candidates.
Single layer graphene is identifiable by (a) a small full width at half maximum (FWHM), (b) a
single Lorentzian curve fit and (c) the peak centre being shifted to lower frequency (~2650 cm-1
using a 633nm excitation source).
0.8
0.6
0.4
0.2
0.0
Resistance = 107.9kΩ
-0.2
0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16
Source-Drain AC Voltage (V)
References:
1. Geim, A.K. and Novoselov, K.S. Nat. Mater. 2007, 6,
183-191.
2. Geim, A.K. and Kim, P. Sci. Am. 2008, 298, 90-97.
3. Novoselov, K.S. Science, 2004, 306, 666.
4. Ferrari, A.C. et al. PRL, 2006, 97, 187401.
We have concluded that our alignment and
wiring protocol is capable of patterning
500nm-sized features with 500nm alignment
accuracy. Furthermore, this methodology
has been successfully employed in the
fabrication of high-quality graphene
devices. Future work will focus on graphene
FET measurements and the interactions of
graphene and molecules. Long term goals
include tuning the electronic properties of
graphene with molecules to optimize more
complex devices such as photovoltaics or
light-emitting diodes.
Acknowledgments:
Jon Rudge, Uvic Nanofabrication
Adam Schuetze, Uvic Advanced Microscopy Facility
NSERC
Canadian Foundation for Innovation
BC Knowledge Development Fund