Transcript CSE 477. VLSI Systems Design - University of California

CSE241A
VLSI Digital Circuits
Winter 2003
Recitation 3: Synthesis
CSE241 Synthesis Overview.1
Kahng & Cichy, UCSD ©2003
Logic Synthesis: explained
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Logic synthesis:
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HDL
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Process of transforming Hardware Description Language (HDL)
code into a logic circuit
VDHL
Verilog (we’ll only use Verilog RTL)
The circuitry:
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Structural-level HDL netlist
Components from a technology specific library
CSE241 Synthesis Overview.2
Kahng & Cichy, UCSD ©2003
Logic Synthesis
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Logic synthesis converts a software code into a connected set a
standard cells
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Real cell properties must be accounted in order to insure that
the actual circuit will perform correctly:
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Propagation Delay through cells
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Connection Delay between cells
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Load Capacitance
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Drive Resistance
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Slew rate (10%- 90% v)
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Area of Cells
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Clock rates
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Setup & Hold times
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Power Consumption
CSE241 Synthesis Overview.3
Kahng & Cichy, UCSD ©2003
Ideal is converted into Real
Sel
case (Sel)
2'b00
00
B
01
10
10
11
11
: status <= A;
2'b01
: status <= B;
2'b10
: status <= 2'b10;
2'b11
: status <= 2'b11;
endcase
A
status
Mux4x1 1x Drive Strength
Area: 12microns
Max Transition 1.0 ns
Input Pin capacitance: .0015pf
Output Pin Max Load: .45 pf
Cell Delay (A -> Z) with .455pf load
and .5ns slew is .3ns
CSE241 Synthesis Overview.4
Kahng & Cichy, UCSD ©2003
Synthesis Related File Types
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Script file
.scr
Verilog file
.v
Synthesized Verilog file
.sv
VHDL file
.vhd
Synthesized VHDL files
.svhd
EDIF file
.edif
Synopsys database file
.db
Reports
.rpt
Log file(standard for most tools).log
CSE241 Synthesis Overview.5
Kahng & Cichy, UCSD ©2003
Synthesis Related File Types
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Library File
.lib
TCL script file
.tcl
Ambit Library Format file
.alf
Ambit Database file
.adb
Magma Database file
.volcano
Command file
.cmd
Standard Delay Format file
.sdf
Standard Parasitics Exchange
Format
CSE241 Synthesis Overview.6
.spef
Kahng & Cichy, UCSD ©2003
Synthesis Data Flow
HDL
Code
Tech
Library
2
Constraints
1
3
Synthesis
Tool
Gate Level Netlist
CSE241 Synthesis Overview.7
Kahng & Cichy, UCSD ©2003
Step 1: Synthesis Setup
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Setup accomplished through setup files and global shell
variables
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Synopsys (.synopsys_dc.setup & script)
Setup directories (example: Project is called Lab2)
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Script
Reports
Libaries
Verilog
CSE241 Synthesis Overview.8
(/ee260b/ee260b/lab2/script)
(/ee260b/ee260b/lab2/reports)
(/ee260b/ee260b/lab2/libraries) (local)
(/ee260b/ee260b/lab2/src)
Kahng & Cichy, UCSD ©2003
Example of .synopsys_dc.setup
Company
=
“UCSD”
Designer
=
“Ben Cichy”
Technology =
“0.13 micron”
Search_path = search_path + {“.” “./libraries/”}
Target_library = {lsi_10k.db}
Link_library
= {“*” lsi_10k.db}
Symbol_library = {lsi_10k.sdb}
//work library for intermediate files
Define_design_lib
CSE241 Synthesis Overview.9
work
-path work
Kahng & Cichy, UCSD ©2003
Reading a Library

Synopsys: read_db msi_10k.db
•
If the .db library file doesn’t exist then it must be created from
the .lib library file (vendor supplied)
•
•
.lib is readable by the user , .db is internal format
•
Library Compiler
Use library compiler to create the.db.
msi_10k.lib -> msi_10k.db ]
-
[ libcompile
Checks the .lib for errors
Translates to .db
CSE241 Synthesis Overview.10
Kahng & Cichy, UCSD ©2003
Purpose of the Library
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The Library contains the cells of the technology (.18,
.13u)
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Cells are “Building Blocks” for the circuit
Must use technology library for physical properties
Synthesis tools considers properties and function of cells
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The key properties:
-
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Cell delay
Rise/fall transitions
Capacitive load
Drive strength
Area and power
DelayTotal = DelayCell + DelayWire
CSE241 Synthesis Overview.11
Kahng & Cichy, UCSD ©2003
Contents of a Library
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Units (V, A, pW, KOhm, nS, etc)
Default parameters
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Nominal Parameters (PVT)
Operating Conditions
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K Factors
Wireload Models
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Worst Case /Best Case
Scaling factors
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Max transition
Input pin cap
Wireload mode
Operating condition
Max fanout
Estimate for fan-in, fan-out
Look-up table templates
Cells: all properties & attributes, Delay Tables, Rise/Fall
Transition Tables, Power Tables
CSE241 Synthesis Overview.12
Kahng & Cichy, UCSD ©2003
Wireload model
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wire_load("45Kto75K") {
capacitance : 0.000070;
resistance : 0.000042;
area : 0.28;
slope : 40.258665;
fanout_length(1, 40.258865);
fanout_length(2, 80.517750);
fanout_length(3, 120.776600);
fanout_length(4, 161.045450);
fanout_length(5, 241.543200);
fanout_length(6, 322.070900);
fanout_length(7, 402.587600);
}
CSE241 Synthesis Overview.13
Kahng & Cichy, UCSD ©2003
Reading RTL
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Synthesis tool reads the RTL files.
The synthesis tool checks for
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Syntax errors
Enters design into synopsys .db format
Command:
Synopsys: analyze –format verilog –lib work
./src/example.v
CSE241 Synthesis Overview.14
Kahng & Cichy, UCSD ©2003
Generic Tech Generation
Synopsys: elaborate example –arch “BEHAVIORAL” –lib work
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Generates Control Data Flow Graphs (CDFGs)
Performs high level logic optimizations
Performs resource allocation
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Adders
Multipliers
Produces a table of the resources that are used
Generates a hierarchical netlist
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Generic” components (gtech.db)
No timing or electrical properties in the design
Genlib cells
CSE241 Synthesis Overview.15
Kahng & Cichy, UCSD ©2003
Design Error Checking
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Check:
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Warnings and Errors in the log file
Examples of Warnings and Errors:
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Signals missing in sensitivity lists
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Shorted inputs or outputs
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Unused & Undriven inputs and outputs
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Blackboxes
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Dangling, undeclared and undriven wires
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Unsynthesizeable or ignored HDL constructs (# delay, etc.)
- Might need linting tool
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Latches
CSE241 Synthesis Overview.16
Kahng & Cichy, UCSD ©2003
Constrain the Design
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Constraints define the parameters of the block which the synthesis
tool must meet.
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Constraints define the relationships between the block and the rest
of the chip.
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These items are defined:
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Clocks
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Arrival times
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Loading on the output pins
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Drive resistance on the input pins
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Timing exceptions
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Operating Conditions
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Wireload model mode
CSE241 Synthesis Overview.17
Kahng & Cichy, UCSD ©2003
Constraints: Commands
Synopsys
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Clocks
create_clock
Input Delay
set_input_delay
Output Delay
Output Load
set_output_delay
set_load
Input Drive
Resistance
set_driving_cell
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False Paths
set_false_path
Multicycle Paths
set_multicycle_path
Operating
Conditions
set_operating_conditions
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Wireload Model
set_wire_load
CSE241 Synthesis Overview.18
Kahng & Cichy, UCSD ©2003
Constraints: set performance targets
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Synthesized design:
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Bounded by constraints
Input/Output, clk; all bound design
The RTL defines the functionality of design
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The library contains the building blocks for building the design
The constraints tell the synthesis tool the timing and electrical
relationships between the block and the chip
CSE241 Synthesis Overview.19
Kahng & Cichy, UCSD ©2003
Optimization
Optimization:
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The generic netlist
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Iteratively
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Mapped to the cells in the tech library a
Timing is computed (with a clocked design)
Tools restructures design until timing is met
Targets:
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Power
Area
Timing (cycle time)
Note: See Lecture 5 for more details
Command:
Synopsys: compile
CSE241 Synthesis Overview.20
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Timing Reports
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Timing reports:
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Are created in synopsys script
Generate longest paths
Timing: set-up/hold-time violations
Timing not met:
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Reconstrain design
Error in netlist
Too long (depth) logic path
CSE241 Synthesis Overview.21
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Other Reports
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Log file output:
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Area Report
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Command window shows errors per excuted command (gui)
Log file (dc_shell) shows execution trace
Just make sure design is not too large
Don’t try to overoptimize in DC
Hierarchy Report
Library Report
State Machine (FSM) report
CSE241 Synthesis Overview.22
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Final Netlist Generation
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Synopsys:
Write verilog netlist
write –format verilog –hierarchy –output
example.mapped.sv
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Write synopsys database file
write –hierarchy –output example.mapped.db
CSE241 Synthesis Overview.23
Kahng & Cichy, UCSD ©2003
Compilation Strategies
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Top-Down Compilation Strategy
Method: Constraints are applied at the top level and the entire chip
is synthesized.
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Time-Budgeting Compilation Strategy (Bottom-Up Approach)
Method: Constrain and synthesize each sub-block. Then import
results and synthesize top level.
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Compile-Characterize-Write Script-Recompile Strategy (CCWSR)
Method: Apply timing constraints to top level. Let tool propagate
timing constraints to lower level blocks (i.e. let the tool do a timing
budget). Have tool generate a constraint script on the characterized
sub-blocks. Synthesize sub-blocks then synthesize top level block.
CSE241 Synthesis Overview.24
Kahng & Cichy, UCSD ©2003
Top-Down Compilation Strategy
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Advantages
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Only top level constraints are needed.
Better results are achieved because optimization is performed
across the entire design.
Disadvantages
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Long compile times
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If the design contains multiple clocks or generated clocks the
tool doesn’t perform as well
A small change in the design requires that the entire design be
re-synthesized
CSE241 Synthesis Overview.25
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Time-Budgeting Compilation Strategy
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Advantages
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Easier to manage because each sub-block has it’s own
constraint and synthesis scripts.
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A change in a sub-block does not necessary require that other
sub-blocks be resynthesized.
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Multiple and generated clocks are more easily handled.
Disadvantages
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Each block is individually synthesized
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Very tedious and time-consuming to update and maintain
multiple scripts.
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Some critical paths don’t become apparent until top level
compile is performed. (unobservability of critical paths)
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A final incremental compile of entire design may be necessary
in order to remove DRC errors.
May not produce optimal design. Prone to error due to
manually specified time budgets.
CSE241 Synthesis Overview.26
Kahng & Cichy, UCSD ©2003
The Automated Chip Synthesis Approach
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Advantages
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Less CPU memory is needed to do synthesis
Automated Chip Synthesis (ACS) can create subblock
constraint budgets based on the top-level constraints
because budgeting is an integrated part of the ACS flow. It
can see across the hierarchy like the top-down methodology.
Individual scripts are created for each sub-block
Disadvantages
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Tool generated constraint scripts are not very readable
A change in a lower level sub-block requires that the entire
design be re-synthesized
May be difficult to achieve convergence between sub-blocks
because of a “Ping-Pong” effect while synthesizing subblocks.
Synopsys ACS White Paper
CSE241 Synthesis Overview.27
Kahng & Cichy, UCSD ©2003
Synthesizeable Verilog Constructs
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(For Verilog 1997)
always
endcase
module
repeat
and
endmodule
nand
supply0
assign
endfunction
negedge
supply1
begin
endtask
buf
for
nor
tri
bufif0
function
not
wait
bufif1
if
notif0
wand sometimes
case
inout
notif1
while
casex
input
or
wire
casez
integer
output
wor
default
large
parameter
xnor
else
macromodule
posedge
xor
end
medium
reg
CSE241 Synthesis Overview.28
task
Kahng & Cichy, UCSD ©2003
Ignored Keywords
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<delay specifications>
scalared, vectored
small, large, medium
specify
time (some tools treat these as integers)
weak1, weak0, highz0, highz1, pull0, pull1
$keyword (some tools use these to set synthesis
constraints)
wait (some tools support wait with a bounded condition)
CSE241 Synthesis Overview.29
Kahng & Cichy, UCSD ©2003
Unsupported Constructs
 <global variables>
 = = =, != =
 cmos, nmos, rcmos,
rnmos, pmos, rpmos
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deassign
fork, join
 forever, while
 initial
 pullup, pulldown
 release
 repeat
 rtran, tran, tranif0, tranif1, rtranif0, rtranif1
 table, endtable, primitive, endprimitive
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defparam
event
force
CSE241 Synthesis Overview.30
Kahng & Cichy, UCSD ©2003
Common Synthesis Problems
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Latches
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Setup Time Violations/ Hold Time Violations
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Poor Constraints
Only real #s through place and route
Slow run-times
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What are the specifications?
Inaccuracy of Wireload models
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RTL, flip-flop designs
Multiple Clock domains correctly
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Unassagined statements
Flat design
Achieving Timing Closure
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Many problems: constraints, RTL design, library, routing
CSE241 Synthesis Overview.31
Kahng & Cichy, UCSD ©2003
Timing Closure
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Timing problem:
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Can’t reach closure
to rapidly achieve timing closure on a design is a HUGE
PROBLEM for semiconductor industry
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A timing closure problem exists when all timing
violations in a design cannot be eliminated despite
multiple synthesis and place & route iterations
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The timing closure problem occurs for a few reasons
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Poor design practices
Inaccurate wireload models
No placement information used during synthesis; therefore
inaccurate connection delays
CSE241 Synthesis Overview.32
Kahng & Cichy, UCSD ©2003