Transcript Q=1 - UCSD VLSI CAD Laboratory

CSE241A
VLSI Digital Circuits
Winter 2003
Recitation 02: Datapath
and Memory
CSE241 R2 Datapath/Memory.1
Kahng & Cichy, UCSD ©2003
Introduction: Basic Building Blocks

Datapath

Execution units
- Adder, multiplier, divider, shifter



Register file and pipeline registers
Multiplexers, decoders
Memory




Overview
DRAM
SRAM cell
Other types
CSE241 R2 Datapath/Memory.2
Kahng & Cichy, UCSD ©2003
The 1-bit Binary Adder
Cin
A
B
1-bit Full
Adder
(FA)
Cout
G = A&B
P=AB
K = !A & !B
S
A
B
Cin
Cout
S
carry status
0
0
0
0
0
kill
0
0
1
0
1
kill
0
1
0
0
1
propagate
0
1
1
1
0
propagate
1
0
0
0
1
propagate
1
0
1
1
0
propagate
1
1
0
1
0
generate
1
1
1
1
1
generate
S = A  B  Cin
= P  Cin
Cout = A&B | A&Cin | B&Cin (majority function)
= G | P&Cin
 How can we use it to build a 64-bit adder?
 How can we modify it easily to build an adder/subtractor?
 How can we make it better (faster, lower power, smaller)?
CSE241 R2 Datapath/Memory.3
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
FA Gate Level Implementations
A
B Cin
A B Cin
t1
Cout
t0
t2 t1
t0
t2
Cout
S
S
CSE241 R2 Datapath/Memory.4
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Review: XOR FA
Cin
A
S
B
Cout
16 transistors
CSE241 R2 Datapath/Memory.5
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Ripple Carry Adder (RCA)
A3 B3
A2 B2
A1 B1
A0 B0
FA
FA
FA
FA
Cout=C4
S3
S2
S1
C0=Cin
S0
Tadder  TFA(A,BCout) + (N-2)TFA(CinCout) + TFA(CinS)
T = O(N) worst case delay
Real Goal: Make the fastest possible carry path
Max delay = tdelay = tsum + (N-1) tcarry
CSE241 R2 Datapath/Memory.6
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Inversion Property

Inverting all inputs to a FA results in inverted values for
all outputs
A
Cout
B
FA
A
Cin

Cout
S
B
FA
Cin
S
!S (A, B, Cin) = S(!A, !B, !Cin)
!Cout (A, B, Cin) = Cout (!A, !B, !Cin)
CSE241 R2 Datapath/Memory.7
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Exploiting the Inversion Property
A3 B3
A2 B2
A1 B1
A0 B0
FA’
FA’
FA’
FA’
S3
S2
S1
S0
Cout=C4
C0=Cin
inverted cell regular cell
• Minimizes the critical path (the carry chain) by
eliminating inverters between the FAs (will need to
increase the transistor sizing on the carry chain portion of
the mirror adder).
Now need two “flavors” of FAs
CSE241 R2 Datapath/Memory.8
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Fast Carry Chain Design
 The key to fast addition is a low latency carry network
 What matters is whether in a given position a carry is



generated
propagated
annihilated (killed)
Gi = Ai & Bi = AiBi
Pi = Ai  Bi (sometimes use Ai | Bi)
Ki = !Ai & !Bi
 Giving a carry recurrence of
Ci+1 = Gi | PiCi
C1 = G0 | P0C0
C2 = G1 | P1G0 | P1P0 C0
C3 = G2 | P2G1 | P2P1G0 | P2P1P0 C0
C4 = G3 | P3G2 | P3P2G1 | P3P2P1G0 | P3P2P1P0 C0
CSE241 R2 Datapath/Memory.10
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Binary Adder Landscape
synchronous word parallel adders
ripple carry adders (RCA)
carry prop min adders
T = O(N), A = O(N)
signed-digit
adders
fast carry prop
adders
residue adders
T = O(1), A = O(N)
Manchester
carry chain
T = O(N)
A = O(N)
CSE241 R2 Datapath/Memory.11
carry
select
parallel
prefix
conditional
sum
T = O(log N)
A = O(N log N)
carry
skip
T = O(N),
A = O(N)
Kahng & Cichy, UCSD ©2003
Parallel Prefix Adders (PPAs)

Define carry operator € on (G,P) signal pairs
(G’’,P’’) (G’,P’)
G’’
G’
€
where
G = G’’  P’’G’
P = P’’P’
(G,P)

!G
P’’
€ is associative, i.e.,
[(g’’’,p’’’) € (g’’,p’’)] € (g’,p’) = (g’’’,p’’’) € [(g’’,p’’) € (g’,p’)]
€
€
€
CSE241 R2 Datapath/Memory.12
€
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
PPA General Structure

Given P and G terms for each bit position, computing all
the carries is equal to finding all the prefixes in parallel
(G0,P0) € (G1,P1) € (G2,P2) € … € (GN-2,PN-2) € (GN-1,PN-1)

Since € is associative, we can group them in any order

but note that it is not commutative
Pi, Gi logic (1 unit delay)

Measures to consider

Ci parallel prefix logic tree
(1 unit delay per level)




Si logic (1 unit delay)


CSE241 R2 Datapath/Memory.13
number of € cells
tree cell depth (time)
tree cell area
cell fan-in and fan-out
max wiring length
wiring congestion
delay path variation
(glitching)
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Adder Types
 RCA = Ripple Carry
 MCC = Manchester Carry Chain
 CCSkA = Carry-Chain Skip
 VCSkA = Variable Carry Skip
 CCSiA = Carry-Chain Save with Invert
 BK = Brent Kung
 Others: (array type)



Ling-Ling
ELM
Kogge-Stone
CSE241 R2 Datapath/Memory.14
Kahng & Cichy, UCSD ©2003
Adder Speed Comparisons
70
60
RCA
MCC
CCSkA
VCSkA
CCSlA
B&K
50
ns
40
30
20
10
16 bits
CSE241 R2 Datapath/Memory.15
32 bits
Slide courtesy of Mary Jane Irwin, Penn state
64 bits
Kahng & Cichy, UCSD ©2003
Adder Average Power Comparisons
35
30
RCA
MCC
CCSkA
VCSkA
CCSlA
B&K
25
20
Watt
15
10
5
0
16 bits
CSE241 R2 Datapath/Memory.16
32 bits
Slide courtesy of Mary Jane Irwin, Penn state
64 bits
Kahng & Cichy, UCSD ©2003
Power-Delay Product of Adder Comparisons
Power Delay Product
100
80
RCA
MCCA
CCSkA
VCSkA
CCSlA
BKA
60
40
20
0
8 bits
16 bits
32 bits
48 bits
64 bits
From Nagendra, 1996
CSE241 R2 Datapath/Memory.17
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Review: Basic Building Blocks

Datapath

Execution units
- Adder, multiplier, divider, shifter


Multiplexers, decoders
Memory




Overview
DRAM
SRAM cell
Other types
CSE241 R2 Datapath/Memory.18
Kahng & Cichy, UCSD ©2003
Parallel Programmable Shifters
Control
=
Shift amount
Shift direction
Shift type (logical,
arith, circular)
Shifters used in multipliers, floating point units
Consume lots of area if done in random logic gates
CSE241 R2 Datapath/Memory.19
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Shifters - Applications

Linear shifting

Concatenate 2 words (N-bits) and pull out a contiguous N-bit word.
wordA

wordB
wordC
Take an portion of a word and shift to to the left or right
- Multiply by 2M
- Pad the emptied position with 0’s or 1’s
- Arithmetic shifts
– Left shift, pad 0’s
– Right shift, pad 1’s

Barrel shifting


Emptied position filled with bit dropped off.
Rotational shifting… circular convolution.
CSE241 R2 Datapath/Memory.20
Slide courtesy of Ken Yang, UCLA
Kahng & Cichy, UCSD ©2003
A Programmable Binary Shifter
rgt
nop
Ai
Ai-1
CSE241 R2 Datapath/Memory.21
left
Bi
Ai Ai-1 rgt nop left Bi Bi-1
A1
A0
0
1
0
A1
A0
A1
A0
1
0
0
0
A1
A1
A0
0
0
1
A0
0
Bi-1
•Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
A Programmable Binary Shifter
rgt
nop
Ai
Ai-1
CSE241 R2 Datapath/Memory.22
left
Bi
Ai Ai-1 rgt nop left Bi Bi-1
A1
A0
0
1
0
A1
A0
A1
A0
1
0
0
0
A1
A1
A0
0
0
1
A0
0
Bi-1
•Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
4-bit Barrel Shifter
A3
B3
Sh1 = 1
B3B2B1B0 = A3A3A2A1
Sh1
A2
B2
Sh2
A1
B1
Sh3
A0
B0
Sh0
Example: Sh0 = 1
B3B2B1B0 = A3A2A1A0
Sh1
CSE241 R2 Datapath/Memory.23
Sh2
Sh2 = 1
B3B2B1B0 = A3A3A3A2
Sh3 = 1
B3B2B1B0 = A3A3A3A3
Area dominated by
wiring
Sh3
•Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
4-bit Barrel Shifter
A3
B3
Example: Sh0 = 1
B3B2B1B0 = A3A2A1A0
Sh1 = 1
B3B2B1B0 = A3A3A2A1
Sh1
A2
B2
Sh2
A1
B1
Sh2 = 1
B3B2B1B0 = A3A3A3A2
Sh3 = 1
B3B2B1B0 = A3A3A3A3
Sh3
A0
B0
Sh0
Sh1
CSE241 R2 Datapath/Memory.24
Sh2
Area dominated by
wiring
Sh3
•Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
4-bit Barrel Shifter Layout
Widthbarrel
A3
A2
A1
•multiplier
A0
Sh0
Sh1
Only one Sh#
active at a timel
CSE241 R2 Datapath/Memory.25
Sh2
Sh3
Buffer
Widthbarrel ~ 2 pm N
N = max shift distance, pm = metal pitch
Delay ~ 1 fet + N diff caps
•Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Review: Basic Building Blocks

Datapath

Execution units
- Adder, multiplier, divider, shifter, etc.


Register file and pipeline registers
Memories




Overview
SRAM cell
DRAM
Other types
CSE241 R2 Datapath/Memory.26
Kahng & Cichy, UCSD ©2003
Multiplication

Binary multiplication


Same with 2’s complement
Multiplicand(B) = -13
10011
Multiplier(A) = -15
 Sign-extend the negative.
x
10001
--------2’s complement N-bit
111110011
Partial products
numbers
00000
 Rhombus of N partial
00000
products
00000
 Product has 2N number of
10011
bits.
Multiplicand*(20+21+22+…)
10011
 Negative multiplier
= Multiplcand*(1111…)
10011
- Last term is equivalent to 2’s 10011
= -1*Multiplicand
complement.
10011
= 01101
 Sign extension is tricky
---------195
011000011
- Drop 1’s into sign bit if 0’s
- Otherwise invert sign bit.
CSE241 R2 Datapath/Memory.27
Slide courtesy of Ken Yang, UCLA
Nine bits + 1 sign.
Kahng & Cichy, UCSD ©2003
Parallel Multipliers

Each partial product is
independent.

Multiply with 2 steps.



First step: generate partial
products in parallel.
Second step: add the
partial products.
Generating the Partial
Products


A0
B0_N-1
A1
PP00
PP01
PP02
A2
PP10
PP11
PP12
PPI,J = AI AND BJ
Sign bit is a little different.
- SI,N = B(sign)’ NAND
A(sign)
CSE241 R2 Datapath/Memory.28
Slide courtesy of Ken Yang, UCLA
Kahng & Cichy, UCSD ©2003
Multiplier Delay

A function of adder style

Example : Shift + add
Ripple carry adder
Tserial_mult = O(N Tadder) = O(N2)
Shifter + adder (RCA)

Increasing performance


Faster adders  array adders, Carry Select
Tree style multiplication
- Wallace

Radix change (encoding)
- Booth
CSE241 R2 Datapath/Memory.29
Kahng & Cichy, UCSD ©2003
Review: Basic Building Blocks

Datapath

Execution units
- Adder, multiplier, divider, shifter, etc.


Register file and pipeline registers
Memories




Overview
DRAM
SRAM cell
Other types
CSE241 R2 Datapath/Memory.30
Kahng & Cichy, UCSD ©2003
Memories today

Embedded memory on every chip





FIFO – for buffering
Registers – for pipelining and temporary data storage
RAM – temporary data storage (for high throughput)
ROM – storing standard instruction set in micro-controllers,
Power On sequence
More than 70% of chip area is memory

high density, good yield - very important
CSE241 R2 Datapath/Memory.31
Kahng & Cichy, UCSD ©2003
Semiconductor Memories
RWM
NVRWM
ROM
Read Write Memory
Non Volatile
Read Only
Maskprogrammed
Random
Access
Non-Random
Access
EPROM
SRAM
(cache,
register file)
FIFO/LIFO
E2PROM
DRAM
Shift Register
FLASH
Electricallyprogrammed
(PROM)
CAM
CSE241 R2 Datapath/Memory.32
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
A Typical Memory Hierarchy

By taking advantage of the principle of locality:


Present the user with as much memory as is available in the
cheapest technology.
Provide access at the speed offered by the fastest technology.
On-Chip Components
Control
.1’s
100’s
highest
CSE241 R2 Datapath/Memory.33
Instr Data
Cache Cache
ITLB DTLB
Speed (ns):
Size (bytes):
Cost:
RegFile
Datapath
eDRAM
1’s
K’s
Second
Level
Cache
(SRAM)
10’s
10K’s
Slide courtesy of Mary Jane Irwin, Penn state
Main
Memory
(DRAM)
100’s
M’s
Secondary
Memory
(Disk)
1,000’s
T’s
lowest
Kahng & Cichy, UCSD ©2003
Embedded Memory Landscape
Storage
DRAM
Mechanism
Availability 2002
SRAM
Flash
MRAM FRAM OUM
2002
2002
2004
2004
2004
130nm
130nm
150nm
350nm
130nm
100nm
1T-1C
6T
1T
1T-1C
1T-1C
1T-1C
8F2
10F2
10F2
~40F2
20-40F2 6F2
0.14 2
0.16 2
0.19 2
4.9 2
0.68 2 0.06 2
<20ns
<10ns
~80ns (R) <25ns
<10ns
<100ns
Unlimited
Unlimited
1ms (W)
>1E5
>1E15
>1E13
>1E13
Volatile
Volatile
>10yrs
>10yrs
>10yrs
>10yrs
Initial
Feature
size
Cell
Structure
Cell Size
(area)
R/W time
No. of
cycles
Retention
CSE241 R2 Datapath/Memory.34
Kahng & Cichy, UCSD ©2003
Access Time comparison
(Generalized ~.13u)
Type
Time (ns)
RDRAM
30ns
SDRAM
20ns
SRAM
10ns
FLASH
80ns (.15.u)
FRAM
10ns
ROM (read)
50ns
Latency
•Time to read
Bandwidth
•Throughput of system
CSE241 R2 Datapath/Memory.35
Kahng & Cichy, UCSD ©2003
Embedded RAM
 SRAMs and DRAMs
SRAM
DRAM
6-T / 4-T memory cell
Capacitor based storage.
High Density
Low Power – important
requirement for system
on chip
Slower Data Access
Refresh cycles required –
hence high power
Relative transistor sizes
determine Noise Margin
Capacitor size
determines Noise Margin
Fast Access cycles
 Noise Margin


Important figure of merit
Degraded with scaling
CSE241 R2 Datapath/Memory.36
Kahng & Cichy, UCSD ©2003
Review: Basic Building Blocks

Datapath

Execution units
- Adder, multiplier, divider, shifter, etc.


Register file and pipeline registers
Memories


Overview
DRAM
- 1T

SRAM cell
- 6T

Other types
CSE241 R2 Datapath/Memory.37
Kahng & Cichy, UCSD ©2003
Read-Write Memories (RAMs)

Static – SRAM







data is stored as long as supply is applied
large cells (6 fets/cell) – so fewer bits/chip
fast – so used where speed is important (e.g., caches)
differential outputs (output BL and !BL)
use sense amps for performance
compatible with CMOS technology
Dynamic – DRAM






periodic refresh required
small cells (1 to 3 fets/cell) – so more bits/chip
slower – so used for main memories
single ended output (output BL only)
need sense amps for correct operation
not typically compatible with CMOS technology
CSE241 R2 Datapath/Memory.38
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
1T DRAM Cell


To write

Assert wordline and drive 1 or 0 on bitline

Charge stored in cap
bit
word
To read

Precharge bit and assert wordline

Bitline and cap share charge
- Small change in bitline voltage detected by sense amp
MOS cap
- Reads are destructive
– Voltage level in the cell degraded after reads
- Need to refresh (re-write) after each read (done by
sense amp)
CSE241 R2 Datapath/Memory.39
Slide courtesy of Ken Yun, UCSD
Kahng & Cichy, UCSD ©2003
1-Transistor DRAM Cell
WL
WL
M1
Cs
CBL
BL
write
“1”
read
“1”
X
X
BL
Vdd/2
Vdd-Vt
Vdd
sensing
Write: Cs is charged (or discharged) by asserting WL and BL
Read: Charge redistribution occurs between CBL and Cs
Read is destructive, so must refresh after read
CSE241 R2 Datapath/Memory.40
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
1-T DRAM Cell
Capacitor
Metal word line
M1 word
line
SiO2
poly
n+
Field Oxide
n+
poly
Inversion layer
induced by
plate bias
Diffused
bit line
Polysilicon
Polysilicon
plate
gate
(a) Cross-section
(b) Layout
Used Polysilicon-Diffusion Capacitance
Expensive in Area
CSE241 R2 Datapath/Memory.41
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Sense Amplifier
bit’
bit
word
sense
clk
isolation transistor
regenerative amplifier
CSE241 R2 Datapath/Memory.42
Kahng & Cichy, UCSD ©2003
DRAM Cell Observations

DRAM memory cells are single ended (complicates the
design of the sense amp)

1T cell requires a sense amp for each bit line due to
charge redistribution read

1T cell read is destructive; refresh must follow to restore
data

1T cell requires an extra capacitor that must be explicitly
included in the design

A threshold voltage is lost when writing a 1


can be circumvented by bootstrapping the word lines to a higher
value than Vdd
Not usually available on chip, unless analog elements are present
CSE241 R2 Datapath/Memory.43
Kahng & Cichy, UCSD ©2003
6-transistor SRAM Cell
WL
M2
M5
M6
!Q
M1
!BL
CSE241 R2 Datapath/Memory.44
M4
Q
M3
BL
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
SRAM Cell Analysis (Read)
WL=1
M4
M5!Q=0
M6
Q=1
M1
Cbit
Cbit
!BL=1
BL=1
Read-disturb (read-upset): must carefully limit the allowed voltage
rise on !Q to a value that prevents the read-upset condition from
occurring while simultaneously maintaining acceptable circuit
speed and area constraints
CSE241 R2 Datapath/Memory.45
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
SRAM Cell Analysis (Read)
WL=1
M4
M5!Q=0
M6
Q=1
M1
Cbit
Cbit
!BL=1
BL=1
Cell Ratio (CR) = (WM1/LM1)/(WM5/LM5)
V!Q = [(Vdd - VTn)(1 + CR (CR(1 + CR))]/(1 + CR)
CSE241 R2 Datapath/Memory.46
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Read Voltages Ratios
Vdd = 2.5V
VTn = 0.5V
1.2
Voltage Rise on !Q
1
0.8
0.6
0.4
0.2
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
Cell Ratio (CR)
CSE241 R2 Datapath/Memory.47
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
SRAM Cell Analysis (Write)
WL=1
M4
M5!Q=0
Q=1
M6
M1
!BL=1
BL=0
Pullup Ratio (PR) = (WM4/LM4)/(WM6/LM6)
VQ = (Vdd - VTn) ((Vdd – VTn)2 – (p/n)(PR)((Vdd – VTn - VTp)2)
CSE241 R2 Datapath/Memory.48
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Write Voltages Ratios
1
Write Voltage (VQ)
0.8
0.6
Vdd = 2.5V
|VTp| = 0.5V
0.4
p/n = 0.5
0.2
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
Pullup Ratio (PR)
CSE241 R2 Datapath/Memory.49
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Cell Sizing
 Keeping cell size minimized is critical for large caches
 Minimum sized pull down fets (M1 and M3)


Requires minimum width and longer than minimum channel
length pass transistors (M5 and M6) to ensure proper CR
But sizing of the pass transistors increases capacitive load on
the word lines and limits the current discharged on the bit lines
both of which can adversely affect the speed of the read cycle
 Minimum width and length pass transistors


Boost the width of the pull downs (M1 and M3)
Reduces the loading on the word lines and increases the
storage capacitance in the cell – both are good! – but cell size
may be slightly larger
CSE241 R2 Datapath/Memory.50
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
6T-SRAM Layout
M2
VDD
M4
Q
Q
M1
M3
GND
M5
BL
CSE241 R2 Datapath/Memory.51
M6
WL
BL
Slide courtesy of Mary Jane Irwin, Penn state
Kahng & Cichy, UCSD ©2003
Review: Basic Building Blocks

Datapath

Execution units
- Adder, multiplier, divider, shifter, etc.


Register file and pipeline registers
Memories



DRAM
SRAM cell
Other types
CSE241 R2 Datapath/Memory.52
Kahng & Cichy, UCSD ©2003
Non-Volatile Memories (Present)
 Standard ROM


Programmed during fabrication
Diffusion programmable / metal or via programmable options
 One Time Programmable (OTP) ROM
•
Involves blowing of fuses – after fabrication
 Erasable Programmable ROM (EPROM)
•
Erase and Program through UV light application
 Electrically Erasable Programmable ROM (EEPROM)


Programmable by application of high voltage
Involves two supply voltages – normally not a problem for
today’s chips
CSE241 R2 Datapath/Memory.53
Kahng & Cichy, UCSD ©2003
Future Memory Lanscape
 Magneto-resistive RAM (~2004 )

IBM, Motorola, Infineon, Nonvolatile Electronics (NVE)
 Ferro-electric RAM (FRAM/ FeRAM) ( ~ 2004)

Ramtron, Symetrix, Fujitsu, Toshiba, IBM/ Infineon, Samsung,
Motorola, Hitachi, Matsuhita, Micron
 Ovonic Unified Memory (OUM) (~2004)

Ovonyx, Intel, STMicroelectronics, British Aerospace
 Nano-Floating Gate memory ( >2005 )
 Single/ Few electron memories (SET) ( >2007)
 Molecular memories ( >2010 )
CSE241 R2 Datapath/Memory.54
Kahng & Cichy, UCSD ©2003
Next Time
 Recitation 3


Performance coding: Verilog
Synthesis
 Future


Lec #15 full lecture on memories
Recitation:
- memory generators
CSE241 R2 Datapath/Memory.55
Kahng & Cichy, UCSD ©2003