Transcript No Slide Title

Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
The Devices
Revised from Digital Integrated Circuits, © Jan M. Rabaey el, 2003
© Digital Integrated Circuits2nd
Devices
Goal of this chapter

Understand device operation for shortchannel devices
 Present intuitive understanding of device
operation
 Introduction of basic device equations
 Introduction of models for manual analysis
 Introduction of models for Spice/Spectre
simulation
 Analysis of secondary and deep-sub-micron
effects

Understanding MOS transistor parasitics
© Digital Integrated Circuits2nd
Devices
The Diode
B
A
Al
SiO2
p
n
Cross-section of pn -junction in an IC process
A
p
Al
A
n
B
One-dimensional
representation
B
diode symbol
Mostly occurring as parasitic element in Digital ICs
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Devices
Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
n
p
hole drift
electron drift
Charge
Density

x
Distance
+
-
Electrical
Field
(b) Charge density.

x
(c) Electric field.
V
Potential
-W 1
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
W2
x
(d) Electrostatic
potential.
Devices
Diode Current
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Devices
The diffusion current
dominates the drift
component. The carriers
traverse the depletion region
and are injected into to the
neutral n and p regions
(become minority carriers)
pn (W2)
Forward Bias (minority carrier concen.)
pn0
Lp
np0
p-region
-W1 0
Typically avoided in Digital ICs
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W2
n-region
x
diffusion
Devices
Reverse Bias (minority carrier concen.)
The drift current dominates
the diffusion component.
Barrier raised and almost no
current from n to p.
pn0
np0
p-region
-W1 0
W2
x
n-region
diffusion
drift
The Dominant Operation Mode for diode
in CMOS VLSI design
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Devices
Models for Manual Analysis
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Devices
Junction Capacitance
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Devices
Diffusion Capacitance
Caused by charge-storage effects of the
minority carriers (in Forward-bias only)
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Devices
Secondary Effects
ID (A)
0.1
0
–0.1
–25.0
–15.0
–5.0
0
5.0
VD (V)
Avalanche Breakdown
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Devices
Diode Model
RS
+
VD
ID
CD
-
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Devices
SPICE Parameters
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Devices
What is a Transistor?
A Switch!
An MOS Transistor
VGS  V T
|VGS|
Ron
S
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D
Devices
The MOS Transistor
Polysilicon
© Digital Integrated Circuits2nd
Aluminum
Devices
MOS Transistors -Types and Symbols
D
D
G
G
S
S
NMOS
NMOS
D
G
G
S
PMOS
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D
B
S
NMOS with
Bulk Contact
Devices
Threshold Voltage: Concept
+
S
VGS
D
G
-
n+
n+
n-channel
Depletion
Region
p-substrate
B
The semiconductor surface inverts to n-type material (strong inversion)
A continuous n-type channel is formed
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Devices
The Threshold Voltage
The value of VGS where strong inversion occurs is called the threshold voltage VT
Fermi potential
When VSB=0 (always has
to be larger than -0.6V to
back bias the pn-junction)
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Devices
The Body Effect
0.9
0.85
0.8
0.75
VT (V)
0.7
0.65
0.6
0.55
0.5
0.45
0.4
-2.5
-2
-1.5
-1
V
BS
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-0.5
0
(V)
Devices
Current-Voltage Relations
A good transistor
6
x 10
-4
VGS= 2.5 V
5
Resistive
Saturation
4
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
VGS= 1.5 V
1
0
Quadratic
Relationship
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
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Devices
Transistor in Linear
VGS
VDS
S
G
n+
–
V(x)
<VGS-VT
ID
D
n+
+
L
x
p-substrate
B
A continuous conductive channel
MOS transistor and its bias conditions
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Devices
Transistor in Saturation
VGS
VDS > VGS - VT
G
D
S
n+
-
VGS - VT
+
n+
Pinch-off
constant
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Devices
Current-Voltage Relations
Long-Channel Device
Mobility (e.g. electron velocity)
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Devices
A model for manual analysis
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Devices
Current-Voltage Relations
The Deep-Submicron Era
2.5
x 10
-4
VGS= 2.5 V
Early Saturation
2
VGS= 2.0 V
ID (A)
1.5
VGS= 1.5 V
1
0.5
0
Linear
Relationship
VGS= 1.0 V
0
0.5
1
1.5
2
2.5
VDS (V)
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Devices
u n (m/s)
Velocity Saturation
The critical field at which
saturation occurs depends
on both doping levels and
vertical electrical field.
Typically 1 to 5v/um for .
(2V across 0.25µm channel).
usat = 105
Constant velocity (hole and electron)
Constant mobility (slope = µ)
c = 1.5
© Digital Integrated Circuits2nd
 (V/µm)
Devices
Perspective
When increasing the VDS, the electrical field in the channel
ultimately reaches the critical value and the carriers at the drain
become velocity saturated (gives a early saturation at VDSAT).
ID
Long-channel device
VGS = VDD
Short-channel device
V DSAT
© Digital Integrated Circuits2nd
VGS - V T
VDS
Devices
ID versus VGS
-4
6
x 10
-4
x 10
2.5
5
2
4
linear
quadratic
ID (A)
ID (A)
1.5
3
1
2
0.5
1
0
0
quadratic
0.5
1
1.5
VGS(V)
Long Channel
© Digital Integrated Circuits2nd
2
2.5
0
0
0.5
1
1.5
2
2.5
VGS(V)
Short Channel
Devices
ID versus VDS
-4
6
-4
x 10
VGS= 2.5 V
x 10
2.5
VGS= 2.5 V
5
2
Resistive Saturation
ID (A)
VGS= 2.0 V
3
VDS = VGS - VT
2
1
VGS= 1.5 V
0.5
VGS= 1.0 V
VGS= 1.5 V
1
0
0
VGS= 2.0 V
1.5
ID (A)
4
VGS= 1.0 V
0.5
1
1.5
VDS(V)
Long Channel
© Digital Integrated Circuits2nd
2
2.5
0
0
0.5
1
1.5
2
VDS(V)
Short Channel
Devices
2.5
A unified model for manual analysis of
short-channel devices
Linear (Resistive)
VDS < VDSAT
Saturated (Constant Current) VDS  VDSAT
G
S
D
B
© Digital Integrated Circuits2nd
Devices
Simple Model versus SPICE
2.5
x 10
-4
VDS=VDSAT
2
Velocity
Saturated
ID (A)
1.5
Linear
1
VDSAT=VGT
0.5
VGT<VDSAT
Saturated
0
0
0.5
1
1.5
2
2.5
VDS (V)
© Digital Integrated Circuits2nd
Devices
A PMOS Transistor
Assume all variables
negative!
-4
0
x 10
VGS = -1.0V
-0.2
VGS = -1.5V
ID (A)
-0.4
-0.6
-0.8
-1
-2.5
VGS = -2.0V
VGS = -2.5V
-2
-1.5
-1
-0.5
0
VDS (V)
© Digital Integrated Circuits2nd
Devices
Transistor Model
for Manual Analysis
© Digital Integrated Circuits2nd
Devices
The Transistor as a Switch
VGS  V T
Most time spent between here
when discharging
Ron
S
D
ID
V GS = VD D
Rmid
R0
V DS
VDD/2
© Digital Integrated Circuits2nd
VDD
Devices
The Transistor as a Switch
where I DSAT
7
x 10
W
k
L
'
5
2

VDSAT 
 (VDD  VT )VDSAT 


2 

6
5
Req (Ohm)
• R is inversely proportional to W/L
4
• No significant reduction when VDD
is much larger than VT+VDSAT/2
3
2
• VDD can not be too small (e.g.
close to VT), otherwise resistance is
very large
1
0
0.5
1.5
1
V
© Digital Integrated Circuits2nd
DD
2
2.5
(V)
Devices
The Transistor as a Switch
© Digital Integrated Circuits2nd
Devices
MOS Capacitances
Dynamic Behavior
• Dynamic behavior is a function of time for the transistor
to charge/discharge the parasitic capacitances
• Parasitic includes
 intrinsic capacitance of the device
load capacitance by the fanout gates and wires
• Intrinsic capacitance have three sources
basic MOS structure
channel charge
depletion region (of reversed-biased pn-junction at
drain/source)
© Digital Integrated Circuits2nd
Devices
Dynamic Behavior of MOS Transistor
G
CGS
CGD
D
S
CGB
CSB
CDB
B
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Devices
1. The Gate Capacitance: overlap capacitance
Polysilicon gate
Lateral diffusion
CGSO=CGDO=
Source
Drain
xd
n+
xd
Ld
W
Cox Xd W=COW
n+
Gate-bulk
overlap
Top view
Gate oxide
tox
n+
Leff
n+
Cross section view
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Devices
2. The Gate Capacitance: channel capacitance
G
G
CGC
CGC
D
S
G
Cut-off
CGC
D
S
Resistive
D
S
Saturation
Most important regions in digital design: saturation and cut-off
© Digital Integrated Circuits2nd
Devices
Gate Capacitance
Discontinuity at around VT
CG C
WLC ox
WLC ox
CG C
=
WLC ox
2
CGC B
C G CS = CG CD
Capacitance as a function of VGS
(with VDS = 0) in linear region
© Digital Integrated Circuits2nd
WLC ox
3
+
CGCD
2
VG S
2WLC ox
CG CS
0
VDS /(VVGDSAT
S-VT)
1
Capacitance as a function of the
degree of saturation (VGS>VT)
Devices
Measuring the Gate Cap using simulator
-16
×10
3 102 16
10
I
I=CG(VGS) dVGS/dt
for VDS=0
© Digital Integrated Circuits2nd
9
Gate Capacitance (F)
V GS
8
7
6
5
4
3
2
2 2 2 1.5 2 1 2 0.5 0 0.5 1
V GS (V)
1.5 2
Devices
3. Junction Capacitance
Channel-stop implant
N A
Side wall
Source
ND
W
Bottom
xj
Side wall
LS
Channel
Substrate N A
Junction capacitance
per unit length
Junction capacitance per unit area
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No channel side
Devices
Junction Capacitance
• Both Cj and Cjsw are non-linear and depends on the bias voltage.
• Keep large reverse-biased voltage for PN junction
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Devices
Capacitances in 0.25 mm CMOS
process
© Digital Integrated Circuits2nd
Devices
The Sub-Micron MOS Transistor
 Threshold
Variations
 Sub-threshold
 Parasitic
© Digital Integrated Circuits2nd
Conduction
Resistances
Devices
Threshold Variations due to DIBL
VT
VT
Long-channel threshold
L
Threshold as a function of
the length (for low VDS )
Low VDS threshold
VDS
Drain-induced barrier lowering (DIBL)
(for very small L )
In traditional derivation of VT, the channel depletion region is assumed to
mainly originate from gate voltage, which neglects the already depleted
region in the source/drain area. This gives more error in case of shorter
channel length.
© Digital Integrated Circuits2nd
Devices
Threshold Variations due to Hot-carrier
• In short-channel devices, the increasing electric field
causes increasing velocity of electron (until velocity
saturation).
• Electron become too “hot”, often trapped in the oxide,
which changes the threshold voltage.
• Hot-carrier effects typically increase threshold of
NMOS, but decrease that of PMOS?
• This complicate the design and leads to long-term
reliability problem.
© Digital Integrated Circuits2nd
Devices
Sub-Threshold Conduction
The Slope Factor
-2
10
Linear
-4
I D ~ I 0e
10
-6
Quadratic
CD
, n  1
Cox
S is DVGS for ID2/ID1 =10
ID (A)
10
qVGS
nkT
-8
10
-10
Exponential
-12
VT
10
10
0
0.5
1
1.5
2
2.5
Typical values for S:
60 .. 100 mV/decade
VGS (V)
© Digital Integrated Circuits2nd
Devices
Sub-Threshold ID vs VGS
I D  I 0e
qVGS
nkT
qV
 DS

1  e kT






VDS from 0 to 0.5V
© Digital Integrated Circuits2nd
Devices
Sub-Threshold ID vs VDS
I D  I 0e
qVGS
nkT
qV
 DS

1  e kT



1    VDS 


VGS from 0 to 0.3V
© Digital Integrated Circuits2nd
Devices
Summary of MOSFET Operating
Regions (sub-micron design)
 Strong
Inversion VGS > VT
 Linear (Resistive) VDS < VDSAT
 Saturated (Constant Current) VDS  VDSAT
 Weak
Inversion (Sub-Threshold) VGS  VT
 Exponential in VGS with linear VDS dependence
© Digital Integrated Circuits2nd
Devices
Parasitic Resistances
Polysilicon gate
LD
G
Drain
contact
D
S
RS
W
VGS,eff
RD
Drain
© Digital Integrated Circuits2nd
Devices
Latch-up
To Backbias pn junction, body of
PMOS connected to Vdd and body of
NMOS to GND
• Parasitic bipolar transistors exist and form positive
feedback
• To cope with it, minimize the Nwell resistance and Psub
resistance
• Place as many N-Well and Substrate contacts as possible
© Digital Integrated Circuits2nd
Devices