Transcript No Slide Title

Sequential Logic
Inputs
Outputs
COMBINATIONAL
LOGIC
Current State
Registers
Q
Next state
D
CLK
2 storage mechanisms
• positive feedback
• charge-based
© Digital Integrated Circuits2nd
Design Methodologies
A simple example of sequential design
A one-input, one-output system receives a binary
sequence (one bit at each clock cycle) and produces
another binary sequence such that the output is 1
whenever a leading subsequence of odd 0s and odd 1s
is recognized in the input sequence. For example, the
input sequence of
01101010010001111110000100…… causes the output
01000100010100000001010000.
© Digital Integrated Circuits2nd
Design Methodologies
Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic
VLSI Design
Methodologies
Revised from Digital Integrated Circuits, © Jan M. Rabaey el
© Digital Integrated Circuits2nd
Design Methodologies
Design Abstraction Levels
SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
S
n+
© Digital Integrated Circuits2nd
D
n+
Design Methodologies
10,000,000
Logic Transistors/Chip
100,000,000
.10m 1,000,000
Transistor/Staff Month
10,000,000
100,000
.35m
10,000
100,000
1,000
10,000
X
100
X x
2.5m
1,000,000
58%/Yr. compound
Complexity growth rate
10
X X
X
1,000
X
100
21%/Yr. compound
Productivity growth rate
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
10
1981
1
Productivity (Trans./Staff-Month)
Logic Transistors per Chip (K)
The Design Productivity Challenge
 A growing gap between design complexity and design productivity
 Designing a multi-million transistor circuit is not possible without
good design methodologies and computer tools
Source: sematech97
© Digital Integrated Circuits2nd
Design Methodologies
INPUT/OUTPUT
A Simple Processor
MEMORY
CONTROL
DATAPATH
 These components occurs in almost all processors
 Datapath is core of the processor. A typical datapath
consists of logic units (AND, OR, XOR etc) and arithmetic
operators (ADDER, MULTIPLIER, COMPARATOR,
SHIFTER etc)
 Control unit can be viewed as a finite state machine.
 Memory stores data and instructions.
© Digital Integrated Circuits2nd
Design Methodologies
INPUT/OUTPUT
A Simple Processor
MEMORY
CONTROL
DATAPATH
 What might be abstracted away from the schematic is
interconnection networks, such as on-chip buses, clock
and power distribution networks.
 For a long time, interconnection network was a
afterthought, but due to technology migration,
interconnects presents capacitive, resistive and inductive
effects, which might affect the system performance.
© Digital Integrated Circuits2nd
Design Methodologies
A System-on-a-Chip: Example
The simple structure shown in previous slide can be
repeated many times on silicon, e.g. a IC chip for HDTV
© Digital Integrated Circuits2nd
Courtesy: Philips
Design Methodologies
Impact of Implementation Choices
 Choosing an effective implementation approach
strongly depends on the function of the modules
under consideration.
 The choice of implementation can have a
tremendous effect on the quality of the final product.
 A design with flexibility is very attractive from
application point of view. But it comes at a price in
both performance and power efficiency.
 Providing flexibility also means additional
hardware overhead.
 Hardware/software co-design (partitioning, task
scheduling, resource allocation etc)
© Digital Integrated Circuits2nd
Design Methodologies
None
© Digital Integrated Circuits2nd
1-10
Embedded microprocessor
Configurable/Parameterizable
10-100
Hardwired custom
Energy Efficiency (in MOPS/mW)
100-1000
Domain-specific processor
(e.g. DSP)
Impact of Implementation Choices
0.1-1
Somewhat
flexible
Fully
flexible
Flexibility
(or application scope)
Design Methodologies
Design Methodology
• Design process traverses iteratively between three abstractions:
behavior, structure, and geometry
• More and more automation for each of these steps
© Digital Integrated Circuits2nd
Design Methodologies
Implementation Choices
Digital VLSI Implementation Approaches
Custom
Semicustom
Cell-based
Standard Cells
Compiled Cells
Ma cro Cells
Array-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
A number of distinct implementation approaches
ranging from high-performance, handcrafted design to
fully programmable medium-to-low performance design
© Digital Integrated Circuits2nd
Design Methodologies
The Custom Approach
 When performance or design density is of primary
importance, handcrafting the design (at both logic
level and layout level) seems to be the only option.
 The labor–intensive nature of custom design
translates into a high cost and long time to market.
So, it should be used only under some conditions.
 With continuous progress in design automation
tools and rapid increase of circuit complexity, fullcustom design is reducing.
 In fact, library cell design is the only area where
custom design still thrives today.
 Design support/assistance tools are needed.
© Digital Integrated Circuits2nd
Design Methodologies
The Custom Approach
Intel 4004
© Digital Integrated Circuits2nd
Courtesy Intel
Design Methodologies
Transition to Automation and Regular Structures
Intel 4004 (‘71)
Intel 8080
Intel 8286
© Digital Integrated Circuits2nd
Intel 8085
Intel 8486
Courtesy Intel
Design Methodologies
Implementation Choices
Digital VLSI Implementation Approaches
Custom
Semicustom
Cell-based
Standard Cells
Compiled Cells
Ma cro Cells
Array-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
A number of distinct implementation approaches
ranging from high-performance, handcrafted design to
fully programmable medium-to-low performance design
© Digital Integrated Circuits2nd
Design Methodologies
Cell-based Design
 Since custom-design approach proves to be prohibitively
expensive, a wide variety of design approaches have been
introduced to shorten and automate the design process.
 The idea behind cell-based design is to reduce the
implementation effort by reusing a library of limited cells.
 The advantage of the approach is that the cells only need
to be designed and verified once for a given technology,
and can be reused many times.
 The disadvantage is that constrained nature of the library
reduces the possibility of fine-tuning the design.
 Cell-based approaches can be partitioned into a number
of classes depending on the granularity of the library
elements.
© Digital Integrated Circuits2nd
Design Methodologies
Cell-based Design (or standard cells)
Standard cell approach standardizes the design entry
level at the logic gate.
 Cells are placed in
rows that are
separated by routing
channels. This requires
that all cells have
equal height.
 Routing channel
requirements are
reduced by
feedthrough cells and
more interconnect
layers (three
dimensional designs)
© Digital Integrated Circuits2nd
Design Methodologies
Standard Cell — Example
Today’s standard cell
typically employs
many versions of
each cell, sized for
different driving
strengths, as well as
performance and
power consumption
level. It is left to
synthesis tools to
select the correct
cells.
[Brodersen92]
© Digital Integrated Circuits2nd
Design Methodologies
Standard Cell – The New Generation
Cell-structure hidden under interconnect Layers (more interconnect
layers). Only a small fraction of the area is wasted for interconnect.
© Digital Integrated Circuits2nd
Design Methodologies
Standard Cell - Example
3-input NAND cell
(from ST Microelectronics 0.18um):
C = Load capacitance
T = input rise/fall time
© Digital Integrated Circuits2nd
Design Methodologies
A Historical Perspective: the PLA
Product terms
x0 x1
x2
AND
plane
OR
plane
f0
x0
© Digital Integrated Circuits2nd
x1
f1
x2
Design Methodologies
Two-Level Logic
Every logic function can be
expressed in sum-of-products
format (AND-OR)
minterm
Inverting format (NORNOR) more effective
© Digital Integrated Circuits2nd
Design Methodologies
PLA Layout – Exploiting Regularity
And-Plane
V DD
x0 x0 x1 x1 x2 x2
Pull-up devices
© Digital Integrated Circuits2nd
Or-Plane
f
GND
f0 f1
Pull-up devices
Design Methodologies
Breathing Some New Life in PLAs
River PLAs

BUFFER
PRE-CHARGE

A cascade of multiple-output PLAs.
Adjacent PLAs are connected via river routing.
PRE-CHARGE
BUFFER
PRECHARGE
BUFFER
PRE-CHARGE
BUFFER
PRE-CHARGE
BUFFER
PRE-CHARGE
BUFFER
PRECHARGE
BUFFER
BUFFER
PRE-CHARGE
• No placement and routing needed.
• Output buffers and the input buffers
of the next stage are shared.
Courtesy B. Brayton
© Digital Integrated Circuits2nd
Design Methodologies
Compiled Cell / Automatic Cell Generation
Customized cells are still attractive, hence automated
cell generation with adjusted sizes is needed
Initial transistor
geometries
Placed
transistors
© Digital Integrated Circuits2nd
Routed
cell
Compacted
cell
Courtesy Acadabra
Finished
cell
Design Methodologies
Macro/Mega Modules and IP blocks
 Standardizing at the logic-gate level is attractive
for random logic functions, but it turns out to be
inefficient for more complex structures such as data
paths, memory, microprocessor etc.
 By capturing the specific nature of some larger
blocks, implementations can be obtained that
outperform the standard cell approach.
 Cells with a complexity that surpasses what is
found in a typical standard cell library are called
macrocells/megacells.
 Macrocells can also be identified as hard macro or
soft macro.
© Digital Integrated Circuits2nd
Design Methodologies
Hard macrocell
 A hard macro cell represents a module with a given
functionality and a pre-determined physical design.
 In essence, a hard macro represents a custom
design of the requested function (in some cases with
parameterization)
 The advantage of the hard macro is that it brings
with it all the good properties of custom design, and
can be reused many times.
 The disadvantage is that it is hard to port the design
to other technologies.
© Digital Integrated Circuits2nd
Design Methodologies
A hard parameterized macrocell
25632 (or 8192 bit) SRAM in 0.18um technology
Generated by hard-macro module generator/compiler
© Digital Integrated Circuits2nd
Design Methodologies
Soft MacroModules
Soft macro represents a module with a given
functionality without a specific implementation, which
may vary from instance to instance. It relies more on
the semi-custom design approaches. (Mostly need
standard cell at lower level).
© Digital Integrated Circuits2nd
Synopsys Design Compiler
Design Methodologies
“Intellectual Property”
 Nowdays, with increasing complexity, circuits are built
with more and more reusable building blocks of
increasing complexity.
 Typically, these modules are acquired from third-party
vendors. Macrocells distributed in this way are called
Intellectual Property (IP).
 Good examples of IP are embedded microprocessors
and microcontrollers, DSP processors, FFT module, filter
modules, error-correction modules, encoding and
decoding modules, etc.
 Design of a complex system is becoming an exercise
of reuse in different levels of granularity. Future system
will use a blend of design styles and design modules.
© Digital Integrated Circuits2nd
Design Methodologies
A Protocol Processor for Wireless
Soft macrocells
IP block
© Digital Integrated Circuits2nd
Custom module
Design Methodologies
Semicustom (cell-based) Design Flow
Design Capture
Behavioral
HDL
Design Iteration
Pre-Layout
Simulation
Structural
Logic Synthesis
Floorplanning
Post-Layout
Simulation
Placement
Circuit Extraction
Routing
Tape-out
© Digital Integrated Circuits2nd
(Thermal, timing,
noise analysis)
Cadence
Encounter
(Synopsys
design
compiler)
Physical
Cadence
Encounter
Cadence
Primetime
Design Methodologies
The “Design Closure” Problem
At deep sub-micron, layout parasitics plays an important
role. A design is forced to go though a number of
iterations to have all timing constraints met. This is
called “timing closure”.
Iterative Removal of Timing Violations (white lines)
© Digital Integrated
Circuits2nd
Courtesy Synopsys
Design Methodologies
Integrating Synthesis with
Physical Design
RTL (Timing) Constraints
Physical Synthesis
Macromodules
Fixed netlists
Netlist with
Place-and-Route Info
Place-and-Route
Optimization
© Digital Integrated Circuits2nd
Artwork
Design Methodologies
Implementation Choices
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Standard Cells
Compiled Cells
Ma cro Cells
Array-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
A number of distinct implementation approaches
ranging from high-performance, handcrafted design to
fully programmable medium-to-low performance design
© Digital Integrated Circuits2nd
Design Methodologies
Late-Binding Implementation
Array-based
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
 All design methodologies discussed thus far require a
complete run through design and fabrication process,
which might lengthen time-to-market.
 Consequently, a number of alternative implementation
approaches are proposed that do not require a complete
run through the manufacturing process, or they avoid
dedicated processing completely.
© Digital Integrated Circuits2nd
Design Methodologies
Pre-diffused Gate Arrays / Sea-of-gates
 In this approach, batches of wafers containing arrays
of primitive cells or transistors are manufactured by the
vendors.
 All fabrication steps needed to make the transistors
are standardized and executed without regard to the
final application.
 To transform these uncomitted wafers to an actual
design, only the desired interconnections have to be
added.
© Digital Integrated Circuits2nd
Design Methodologies
Pre-diffused Gate Arrays: Sea-of-gates
The primary challenge is to determine the composition
of primitive cell and the size of transistors such that the
gate array template can be utilized to a maximal extent
polysilicon
over a wide range of designs.
VD D
rows of
uncommitted
cells
metal
possible
contact
GND
In 1 In 2
Uncommited
Cell
In 3 In4
routing
channel
Committed
Cell
(4-input NOR)
Out
Contact predefined
© Digital Integrated Circuits2nd
Design Methodologies
Sea-of-gate Primitive Cells
Oxide-isolation
PMOS
PMOS
NMOS
NMOS
NMOS
Using oxide-isolation
© Digital Integrated Circuits2nd
Using gate-isolation
Design Methodologies
Example: Base Cell of Gate-Isolated GA
From Smith97
© Digital Integrated Circuits2nd
Design Methodologies
Example: register in Gate-Isolated GA
From Smith97
© Digital Integrated Circuits2nd
Design Methodologies
Sea-of-gates
Utilization factor varies depending on the application.
Random Logic
Memory
Subsystem
LSI Logic LEA300K
(0.6 mm CMOS)
© Digital Integrated Circuits2nd
Courtesy LSI Logic
Design Methodologies
The return of gate arrays?
Via programmable gate array
(VPGA)
Via-programmable cross-point
metal-5
metal-6
programmable via
Exploits regularity of interconnect
© Digital Integrated Circuits2nd
[Pileggi02]
Design Methodologies
Pre-wired Arrays
 Pre-diffused arrays offer a faster road to
implementation, but it would be even better if
dedicated manufacturing steps could be avoided.
 This leads to pre-processed die that can be
programmed in the file to implement any logic function,
called Field Programmable Logic Array (FPGA).
 Two main issues in FPGA: how to implement the
programmability and how to store the programmability
© Digital Integrated Circuits2nd
Design Methodologies
Pre-wired Arrays

Programming Technique (how to store?)
 Fuse-based (program-once)
 Non-volatile EEPROM based (read-only memory)
 RAM based
© Digital Integrated Circuits2nd
Design Methodologies
Fuse-Based FPGA
antifuse polysilicon
n+ antifuse diffusion
2l
Open by default, closed by applying current pulse, only
one-time programmable
From Smith97
© Digital Integrated Circuits2nd
Design Methodologies
Nonvolatile EEPROM FPGA
 Memory stores its value even when power is down
(flash memory or EEPROM)
 Once programmed, the logic remains functional until
a new programming round.
 Extra complexity and cost
From Smith97
© Digital Integrated Circuits2nd
Design Methodologies
Non-volatile memory

the transistor has two gates, a control gate (CG) and a floating
gate (FG) insulated all around by an oxide layer.

The FG is interposed between the CG and the MOS channel.

Because the FG is electrically isolated by its insulating layer,
any electrons placed on it are trapped there and, under
normal conditions, will not discharge for many years.

When the FG holds a charge, it partially cancels the electric
field from the CG, which modifies the VT of the cell.

During read-out, a voltage is applied to the CG, and the
MOSFET channel will become conducting or remain
insulating, depending on the VT of the cell, which is in turn
controlled by charge on the FG. The current flow through the
MOSFET channel is sensed and forms a binary code,
reproducing the stored data.
© Digital Integrated Circuits2nd
Design Methodologies
Non-volatile memory
© Digital Integrated Circuits2nd http://en.wikipedia.org/wiki/Flash_memory Design Methodologies
Volatile RAM FPGA
 By far the most popular approach
 Static RAM used, so lose value when power down.
Thus, a re-loading of the program from an external
permanent memory is needed every time power is on
 Parallel interface is needed for today’s large size
program
From Smith97
© Digital Integrated Circuits2nd
Design Methodologies
Pre-wired Arrays

Programmable Logic (how to implement
programmability?)
For logic function
 Array-Based
 Look-up Table
For interconnect
 Channel-routing
 Mesh networks
© Digital Integrated Circuits2nd
Design Methodologies
Array-Based Programmable Logic
The later two are variants of the first one with one
plane fixed
I5
I4
I3
I2
I1
I0
Programmable
OR array
Programmable AND array
I3
I2
I1
I0
Programmable
OR array
Fixed AND array
O 3O 2O 1O 0
PLA
I5
I4
I3
I2
I1
I0
Fixed OR array
Programmable AND array
O3O2O1O0
PROM
O 3O 2O 1O 0
PAL
Indicates programmable connection
Indicates fixed connection
© Digital Integrated Circuits2nd
Design Methodologies
Programming a PROM
1
X2
X1
x2x1x0
X0
: programmed node
NA NA f 1 f 0
© Digital Integrated Circuits2nd
Design Methodologies
More Complex PAL
i inputs, j minterms/macrocell, k macrocells
© Digital Integrated Circuits2nd
From Smith97
Design Methodologies
2-input MUX
as programmable logic block
Configuration
A
0
F =AS+BS
B
1
S
© Digital Integrated Circuits2nd
A
B
S
F=
0
0
0
0
X
Y
Y
1
1
1
0
X
Y
Y
0
0
1
0
0
1
0
1
1
X
Y
X
X
X
Y
1
0
X
Y
XY
XY
XY
X+ Y
X
Y
1
Design Methodologies
Logic Cell of Actel Fuse-Based FPGA
A
B
1
SA
Y
1
C
D
1
SB
S0
S1
© Digital Integrated Circuits2nd
Design Methodologies
Memory
Look-up Table Based Logic Cell
Out
In
Out
00
00
01
1
10
1
11
0
ln1 ln2
Programmable memory
© Digital Integrated Circuits2nd
Design Methodologies
LUT-Based Logic Cell
4
C1....C4
xx
xxxx
xxxx
xxxx
Bits
control
D4
D3
D2
Logic
function
of
xxx
D1
Logic
functionx
of
xxx
F4
F3
F2
F1
xx
xx
xx
xx
Logic
function
of
xxx
x
xxxxx
Xilinx 4000 Series
© Digital Integrated Circuits2nd
xxxx
xx
x xx x
xx xx
x
x
x
x
Bits
control
xx
xx
xx
xx
xxxx
x xx x
xx
xx xx
H
P
x
x
Multiplexer Controlled
by Configuration Program
Courtesy Xilinx
Design Methodologies
Array-Based Programmable Wiring
M
Interconnect
Point
Programmed interconnection
Input/output pin
Cell
Horizontal
tracks
Vertical tracks
© Digital Integrated Circuits2nd
Design Methodologies
Mesh-based Interconnect Network
Switch Box
Connect Box
Interconnect
Point
© Digital Integrated Circuits2nd
Courtesy Dehon and Wawrzyniek
Design Methodologies
Transistor Implementation of Mesh
© Digital Integrated Circuits2nd
Courtesy Dehon and Wawrzyniek
Design Methodologies
Hierarchical Mesh Network
Use overlayed mesh
to support longer connections
Reduced fanout and reduced
resistance
© Digital Integrated Circuits2nd
Courtesy Dehon and Wawrzyniek
Design Methodologies
Altera MAX
© Digital Integrated Circuits2nd
From Smith97
Design Methodologies
Altera MAX Interconnect Architecture
column channel
row channel
t PIA
LAB1
LAB2
LAB
PIA
t PIA
LAB6
Array-based
(MAX 3000-7000)
© Digital Integrated Circuits2nd
Mesh-based
(MAX 9000)
Courtesy Altera
Design Methodologies
Xilinx 4000 Interconnect Architecture
CLB
12
Quad
8
Single
4
Double
3
Long
2
3
12
4
4
8
Quad
Long
Global
Long
Clock
© Digital Integrated Circuits2nd
4
8
4
Double Single Global
Direct
Connect
Long
2
Carry
Direct
Clock Chain Connect
Courtesy Xilinx
Design Methodologies
RAM-based FPGA
Xilinx XC4000ex
© Digital Integrated Circuits2nd
Courtesy Xilinx
Design Methodologies
About FPGA
 To make array-based approach successful,
advanced software support in terms of cell placement,
signal routing and synthesis is required.
 Programmable logic is at least 10 times less
efficient in terms of energy and performance with
respect to ASIC (Application Specific Integrated
Circuit) and custom designs.
Xilinx XC4000ex
© Digital Integrated Circuits2nd
Courtesy Xilinx
Design Methodologies
Design at a crossroad System-on-a-Chip
Hybrid implementation seems to be the future!
500 k Gates FPGA
MultiSpectral
+ 1 Gbit DRAM
RAM
Imager
Preprocessing
64 SIMD Processor
Array + SRAM
Image Conditioning
100 GOPS
© Digital Integrated Circuits2nd
Analog

mC
system
+2 Gbit
DRAM
Recognition




Embedded applications
where cost, performance,
and energy are the real
issues!
DSP and control intensive
Mixed-mode
Combines programmable
and application-specific
modules
Tools plays crucial role
Design Methodologies
Heterogeneous Programmable Platforms
FPGA Fabric
Embedded memories
Embedded PowerPc
Hardwired multipliers
Xilinx Vertex-II Pro
High-speed I/O
© Digital Integrated Circuits2nd
Courtesy Xilinx
Design Methodologies
Addressing the Design Complexity Issue
Architecture Reuse
Reuse comes in generations
Generation
Reuse element
Status
1st
Standard cells
Well established
2nd
IP blocks
Being introduced
3rd
Architecture
Emerging
4th
IC
Early research
Source: Theo Claasen (Philips) – DAC 00
© Digital Integrated Circuits2nd
Design Methodologies
Architecture ReUse

Silicon System Platform






Flexible architecture for hardware and software
Specific (programmable) components
Network architecture
Software modules
Rules and guidelines for design of HW and SW
Has been successful in PC’s
 Dominance of a few players who specify and control architecture

Application-domain specific (difference in constraints)




Speed (compute power)
Dissipation
Costs
Real / non-real time data
© Digital Integrated Circuits2nd
Design Methodologies
Platform-Based Design
“Only the consumer gets freedom of choice;
designers need freedom from choice”
(Orfali, et al, 1996, p.522)




A platform is a restriction on the space of possible implementation
choices, providing a well-defined abstraction of the underlying
technology for the application developer
New platforms will be defined at the architecture-micro-architecture
boundary
They will be component-based, and will provide a range of choices
from structured-custom to fully programmable implementations
Key to such approaches is the representation of communication
(interconnect) in the platform model
© Digital Integrated Circuits2nd
Source: R. Newton
Design Methodologies
Summary

Digital CMOS Design is kicking and healthy

Who can afford design in the years to come?
Some major design methodology change in
the making!
© Digital Integrated Circuits2nd
Design Methodologies