SKADS Costing
Download
Report
Transcript SKADS Costing
Large gate periphery InGaAs/InAlAs
pHEMT: Measurement and Modelling
for LNA fabrication
B. Boudjelida, A. Sobih, A. Bouloukou, S. Boulay, J.
Sexton, T. Tauqueer, J. Sly and M. Missous
School of Electrical and Electronic Engineering
University of Manchester
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
OUTLINE
•
GOALS
•
•
•
Low Rn
ACTIVE DEVICES
•
•
•
•
•
•
Low Fmin
INTRINSIC PROPERTIES
MODELLING
RESULTS
LNA SIMULATIONS
QUICK ADC UPDATE
CONCLUSIONS
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
Workflow at University of
Manchester
Material assessment
Material growth
DC & RF measurements
Parameter extraction &
device modelling
Process set-up and fabrication
LNA building blocks library
Process set-up
LNA
Fabrication!
LNA circuit design
LNA layout design
(process integration)
LNA testing
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
GOALS
Low Fmin and Low Rn
2
opt s
4Rn
F Fmin
Z 0 1 s 2 (1 s2 )
Four noise parameters
Fmin: the minimum noise factor expected when Γs = Γopt,
Rn: the equivalent noise resistance,
Gopt and Bopt: the real and imaginary parts of the optimal source admittance
Yopt, for which
1 Z 0Yopt
opt
1 Z 0Yopt
For Broad band low noise amplification Need both low Fmin AND low Rn
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
GOALS
Low Fmin and Low Rn
300 K
300 K
200 K
200 K
18 K
Variation of Fmin with frequency and
temperature.
18 K
Variation of Noise Resistance Rn with
frequency and temperature.
(NGST 0.1 x 80 um InGaAs-InAlAs Phemt [*])
Very difficult to achieve low Rn with submicron devices below 2GHz
[*] M.R. Murti et al. IEE Transactions MTT 48(12), 2579, (2000).
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
ACTIVE DEVICES
Increased gate metallisation thickness
The gate metallisation resistance
m
3hLg
[1]
key contributor to gate resistance Rg
For a fixed gate length: increasing gate thickness (h) reduces Rg
AuGe/
Au
δ
Ti/
Au
h
W
m
3hLg N 2
Why reduce it?
AuGe/
Au
Key parasitic contributor
f
Fmin 10log1 k
fT
( g m ( Rs Rg )
Gate thickness h (nm)
Rg (Ohm)
NFmin @ 2GHz (dB)
150
21
1.2
500
2.7
0.6
Comparison between VMBE#1841 transistors made with different gate metallisations
(1x200μm devices, Rg extracted, NFmin calculated for k=3.6)
[1]: G. Vasilescu, Electronic noise and interfering signals, Springer-Verlag Berlin Heindelberg New York, 2005
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
ACTIVE DEVICES
Latest results on Rg and Rn
Rg and Rn extracted from linear and non-linear
models, respectively.
Normal trend for 2-finger devices shows an
increase in Rg with increasing gate size
2-finger topology
Rn decreases with increasing gate size
Use of multi gate finger topology:
• Reduces Rg to about 2 Ohms
• Makes Rg insensitive to gate size
Use of large multi gate finger devices is the
key to:
• Maintaining a low Rg
• Reducing Rn
multi-finger topology
The effect of topology on Rg and Rn XMBE#106
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
ACTIVE DEVICES
Non Linear Modelling
EE-HEMT model generated from IC-Cap
measurements
Transferred to ADS and fitted to
measured data
DC Characteristics Fit the Data very well
Kink effects not included in the model
RF Data (4x200 μm)
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
LNA SIMULATIONS
The use of large inductors (generally used for input matching) on MMIC:
• Large space on chip
• Generate significant series resistance which greatly increases the noise
figure
Avoiding large inductors ??
No input matching?
Off-chip components?
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
LNA SIMULATIONS
Single stage LNA (800 um gate width) with no input matching
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
LNA SIMULATIONS
@ 1.4 GHz
•NF < 0.6dB
Single stage LNA (800 um gate width) with no input matching
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
LNA SIMULATIONS
Single stage LNA (800 µm gate width) with off-chip components.
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
LNA SIMULATIONS
@ 1.4 GHz
•NF < 0.45dB
Single stage LNA (800 µm gate width) with off-chip components.
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
ADC Summary
• AIM: Design and fabrication of a 4bit 4GS/s ADC consuming 100 mW
• Current state-of-the-art : 0.18µm CMOS 4-bit 4GS/s - 220mW [1]
Comparator Design
Transistor Type
(mm2)
Power
(mW)
Power Saving
(%)
1st Generation
55
1,730
-
55 (≠circuit)
1,200
30
1.55
502
71
1.55
350
80
2nd Generation
3rd Generation
(folding)
•
FULL ADC Results to follow shortly.
[1] S. Park, Y. Palaskas, and M. P. Flynn, "A 4GS/s 4b flash ADC in 0.18mm CMOS,“
IEEE Symp. On Circuits and Systems, pp 2330 – 2339, Feb 2006
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA
ADC Basic Building Blocks
Current work
•
Basic Building blocks for the ADC designed using ADS
•
Coplanar waveguide design
•
•
•
•
Differential Amplifier
Ex-Or/OR/AND
Latch
12-Mask procedure
•
•
•
•
HBT (9 masks)
NiCr Resistors (~100 ohms/sq)
3 metal layers
Polyimide dielectric
EX-OR
2nd SKADS Workshop 10-11 October 2007
Complete MMIC
B. BOUDJELIDA
CONCLUSIONS
• Large periphery transistors are needed for low noise resistance Rn and
wide band operation especially at low frequencies (< 2GHz).
• A wide range of large periphery multi-finger InGaAs/InAlAs pHEMTs
have been fabricated (up to 1.2mm gate width).
• Accurate Linear and Nonlinear models have been obtained for these
devices.
•Simulated LNA based on this design yield less than 0.45dB Noise figure
at 1.4GHz even at 1µm gate length!
•4 bit 4GS/s ADC designed, simulated and basic building blocks
fabricated.
• LNA and ADC are being fabricated now.
2nd SKADS Workshop 10-11 October 2007
B. BOUDJELIDA