Transcript SKADS-LOGO

DS4-T1
FRONT-END TECHNOLOGIES
FRONT-END TECHNOLOGIES
Mo Missous
Microelectronics and Nanostructures
School of Electrical and Electronic Engineering
University of Manchester
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
PARTICIPANTS
Manchester :
ASTRON
OPAR
21 July 2015
:
:
InP technologies for LNA and High
Speed ADC.
GaAs LNA ( with OMMIC)
SiGe LNA ( with Philips)
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
AIMS
To develop active semi-conductor devices and rf amplifier systems,
including high speed Analogue to Digital Converters (ADC), optimised
specifically for radio astronomy applications (rather than commercial and
military one).
GOALS
To combine low noise, high linearity and low power dissipation with low cost
manufacturability . Achieving these aims involves a combination of materials
(GaAs, SiGe and InP) and topologies (lithography).
This will require development of customised active device technology, and
the use of novel design techniques.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
Basic Semiconductor Technologies
(MANCHESTER )
Design and Fabrication, using a first generation 1µm optical
lithography process, of Low Noise InGaAs-InAlAs pHEMT
with improved breakdown voltages and with adequate noise
figure (< 35K at 1.4 GHz ).
Design and Fabrication of high Speed InGaAs-InP HBT with
FT > 70 GHz but still based on the same optical lithography
process .
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
•
1.(a) [High Breakdown Voltage/Low noise pHEMT]
1.8
1.6
1.4
1.2
1
0.8
0.6
N.F_1831 (dB)
0.4
N.F_1855 (dB)
0.2
0
0
Figure 1: Comparison of Gate-Source
diode I-V for conventional (VMBE1855)
and newly developed structure
(VMBE1831).
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1
2
3
4
5
6
Figure 2. Comparison of optimum noise figures
of the improved (VMBE1831) and conventional
(VMBE1855) pHEMTs
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
•
1.(b) [Wide Band LNA Designs based on developed pHEMTs]
Figure 3: Wide Band (0.4 -2GHz Feed back Amplifier based on 1 µm InGaAs-InAlAs pHEMT
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
•
1.(b) [Wide Band LNA Designs based on developed pHEMTs]
-Stability (stable 0-30
GHz)
-Noise (NF=1.2 ± 0.3
dB) 0.4-2 GHz
-Gain ( Gain=21± 2 dB)
0.4-2 GHz
Figure 4: Wide Band (0.4 -2GHz Feed back Amplifier based on 1 µm InGaAs-InAlAs
pHEMT, rf characteristics.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
• 2.(a) [High Speed InGaAs-InP HBT]
implementation.
Figure 5: 55m self-aligned HBT (a) Common-emitter output characteristics
(b) Collector current versus fT. Simulated and Measured characteristics
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
• 2.(b) [4 bit 4Gs/s ADC Designs]
AntiAliasing
(1)
Sample and Hold
(2)
Quantiser
(3)
Encoder
(4)
A - buffer
CH - hold capacitor
Figure 6: High Speed Flash ADC building Blocks
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
• 2.(b) [4 bit 4Gs/s ADC Designs]
Figure 7: Captured results from simulation of the comparator array at 4GHz clock
and (a) 0.25GHz and (b) 1GHz input signal frequency
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
• 2.(b) [4 bit 4Gs/s ADC Designs]
The basic building blocks to produce low power ADCs are currently
being investigated. The initial results for the transistors suggest these
can operate effectively at extremely low bias voltages. The
simulations for the comparator of the ADC show promising progress,
providing a relatively low power consumption of 1.73W at larger
geometries. With further optimisation of the epilayer design, transistor
geometry ( 1x3 emitter sizes) and circuit layout, an ultra-low power,
GHz class ADC looks increasingly possible using this technology.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
ASTRON concentrated on the use of existing Integrated Circuit processes with a
strong focus on III/V technologies for the implementation of Low Noise Amplifiers.
3 (a). [ Dual Feedback LNA]
Dual-loop negative feedback amplifiers are suitable for both wideband and low noise
applications. Compared to the conventional inductive-degenerated low noise amplifiers,
the dual-loop feedback amplifier offers well-defined input impedance and signal transfer
function and potentially good noise performance simultaneously.
The dual-loop power-to-power configuration is mostly used for applications that have a
well-defined source and load impedance, since its input impedance depends on the load
and the output impedance depends on the source. The dual-loop power-to-voltage and
power-to-current configurations do not have these limitations and are therefore very
suitable for active antenna applications.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
Figure 8: Schematic and Simulated performance of the dual feedback LNA
This has been implemented in 0.2µm GaAs technology from OMMIC, partner in
SKADS. A very good input impedance match combined with a good noise match
has been achieved. Measurements of the realized device are in progress.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
3 (b). Differential Low Noise Amplifier Design
In order to avoid the need for a balun (balanced-unbalanced) circuit between the antenna
and the LNA, a differential LNA concept has been implemented in InP (NGC) and GaAs
(OMMIC).
The differential LNA can be connected directly to the differential antenna concepts like the
Vivaldi antenna. For the intermitted impedance levels non-50 Ohm impedance can be
selected in order to avoid further ‘matching’ circuitry losses.
Characterization of these circuits is however very complicated. This will be described in
more detail in the DS4-T4 presentation, wide band integrated antennas.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
3 (c). CMOS Low Noise Amplifiers
A standard LNA concept has been implemented in 0.18µm CMOS technology from
UMC. The impedance and noise matching on the input requires an off-chip
transmission line, limiting the frequency band width somewhat. The measured noise
figure reaches the 0.5dB as can be seen from the plot below.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
Figure 9: Simulated and measured results of the CMOS LNA
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
OPAR contribution in DS4-T1 is centered on the use of low cost Si based technologies
for the design of basic building blocks of SKA such as filters and wide band LNAs.
4. (a) Filter design in PICS technology
PICS is a low cost 1µm Silicon technology available from Philips
Semiconductors that offers high quality passives and the ability to achieve a
highly integrated System in Package by using the substrate itself for
interconnecting different dies that may be made from different materials for
building a super-die.
This low cost technology coupled with its capability to achieve high integration
can be very valuable in tackling cost issues for SKA.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
Filter design
Two band pass filters have been designed, a 5th order Tchebytchev band-pass filter
and a high pass filter cascaded with 1 (or 2) low pass filter.
Figure 10: Microphotograph and transmission of the Tchebytchev band-pass filter
Both filters show good agreement with the simulations. Results from this first iteration
are good enough to allow a second step follow up that will use this substrate and a next
iteration of this filter as an interconnect substrate to realize a LNA/filter combination on a
super-die.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
4. (b) SiGe LNA
The QuBiC4G SiGe technology from Philips Semiconductors was used ( 0.25 µm). This
technology exhibits a minimum noise figure NFmin of 0.6 dB at a frequency of 2 GHz.
Another technology, QuBiC4X that is a SiGe:C technology even achieves a NFmin of 0.4 dB.
Its use will be assessed in the next stage.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
In order to assess the potential of Silicon based technologies for wide band LNA, a 300 MHz –
2 GHz amplifier both in single ended and in differential configuration have been designed.
1,20
NF
NFmin
dB
1,10
1,00
0,90
0,80
0,70
0,3 0,5 0,7 0,9 1,1 1,3 1,5 1,7 1,9
frequency (GHz)
Figure 11: Layout and noise figure of the differential 300 MHz – 2 GHz QuBiC4G LNA
The minimum noise figure (0.9 dB @ 2 GHz) is close to the minimum noise figure of the
technology (0.6 dB@ 2 GHz). The noise figure is as low as 0.93 dB around 700 MHz and
is below 1.2 dB from 300 MHz to 2 GHz.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
Sdd11
Sdd21
26,5
Sdd22
-12
25,5
dB
dB
26
25
-17
24,5
-22
24
0,3 0,5 0,7 0,9 1,1 1,3 1,5 1,7 1,9
0,3
0,8
1,3
1,8
frequency (GHz)
frequency (GHz)
Figure 12: Gain and matching of the differential 300 MHz – 2 GHz QuBiC4G LNA
We have demonstrated that it is possible to design a wide band LNA in the 1 dB NF range
with a flat gain and good input and output matching using a low-cost commercially
available 0.25 µm Silicon technology. We hope to decrease still further this value as
technologies with lower NFmin become available.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
Achieved milestones and deliverables
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
Task number
Deliverable
No
Deliverable Name
Ds4-T1
DS4-T1.1
Ds4-T1
Delivered by
Contractor(s)
Planned
(in months)
Achieved
(in months)
Establish benchmark LNA
simulations to provide
performance feedback for
device process
development for various
semiconductor
technologies.
UMAN,
ASTRON
T0+12
12
DS4-T1.2
RF on wafer (RFOW)
measurements on device
wafers fabricated, extract
scaleable equivalent circuit
model.
UMAN
T0+9 to T0+15
12
DS4-T1
DS4-T1.5
ADC Design rule
established and
recommended ADC
architectures selected.
UMAN
T0+1 to T0+12
12
DS4-T1
DS4-T1.3
Design, fabrication and
testing of SiGe band pass
filter using PIC Technology
OPAR
T0+6 to T0+18
12
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Workpackage
/SubTask No
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
NEXT 18 MONTHS STAGE [July 2006 to Jan 2008]
LNA design techniques simulation study – determine optimum design approach,
including consideration of circuit topologies best suited for achieving wide operating
bandwidth, linearity, low noise temperature, high yield and low cost (T0+15 to T0+36).
ADC building blocks design, fabrication and performance (T0+12 to T0+30)
Design, manufacture and test of hybrid LNA using novel discrete devices developed in
programme (two iterations) (T0+18 to T0+24).
Fabricate and test Integrated ADC circuits (T0+18 to T0+30)
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
TABLE 1: Schedule for DS4-T1
The Gantt chart for these tasks remains on target.
21 July 2015
SKADS Workshop 2006
Mo Missous
DS4-T1
FRONT-END TECHNOLOGIES
ACKNOWLEDGEMENTS
Jan Geralt Bij de Vaate
Jaques Pezzani
Joz Sly
James Sexton
A. Bouloukou
A. Sobih
Plus many, many more!
21 July 2015
SKADS Workshop 2006
Mo Missous