Transcript CHAP4-3

Topics

Transistor sizing:
– Spice analysis.
– Logical effort.
Modern VLSI Design 3e: Chapter 4
Copyright  1998, 2002 Prentice Hall PTR
Transistor sizing
Not all gates need to have the same delay.
 Not all inputs to a gate need to have the
same delay.
 Adjust transistor sizes to achieve desired
delay.

Modern VLSI Design 3e: Chapter 4
Copyright  1998, 2002 Prentice Hall PTR
Example: adder carry chain
One stage:
+
ai
bi
ai
bi
+
ci
c i+1
ci+1
ci
ai
ai
bi
bi
ci+1 =ai bi + (ai + bi ) ci
Modern VLSI Design 3e: Chapter 4
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Carry chain optimization
Connect four stages.
 Optimize delay through carry chain by
selecting transistor sizes.

Modern VLSI Design 3e: Chapter 4
Copyright  1998, 2002 Prentice Hall PTR
Case 1
W/L for all stages: n = 0.75/0.5, p = 1.5/0.5
Modern VLSI Design 3e: Chapter 4
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Case 2
Wider pulldowns for first stage XOR, larger first stage inverter:
Modern VLSI Design 3e: Chapter 4
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Case 3
Larger transistors in second and third stages:
Modern VLSI Design 3e: Chapter 4
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Inter-stage effects in transistor
sizing

Increasing a gate’s drive also increases the
load to the previous stage:
Larger
load
Modern VLSI Design 3e: Chapter 4
Larger
drive
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Logical effort



Logical effort is a gate delay model that takes
transistor sizes into account.
It is measured by the ratio of the input capacitance
of a gate to the input capacitance of an inverter
that delivers the same output current. (From Weste
and Harris, p. 166, CMOS, VLSI Design.)
Allows us to optimize transistor sizes over
combinational networks.
Modern VLSI Design 3e: Chapter 4
Copyright  1998, 2002 Prentice Hall PTR
Logical effort gate delay model
Gate delay is measured in units of
minimum-size inverter delay t.
 Gate delay formula:

– d = f + p.
Effort delay f is related to gate’s intrinsic
work to compute its logic output.
 Parasitic delay p depends on gate’s
structure.

Modern VLSI Design 3e: Chapter 4
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Effort delay

Effort delay has two components:
– f = gh.

Electrical (fanout) effort h is determined by
gate’s load:
– h = Cout/Cin

Logical effort g is determined by gate’s
function and structure.
Modern VLSI Design 3e: Chapter 4
Copyright  1998, 2002 Prentice Hall PTR
Logical effort
1 input
2 inputs
3 inputs
4 inputs
n inputs
NAND
4/3
5/3
6/3
(n+2)/3
NOR
5/3
7/3
9/3
(2n+1)/3
mux
2
2
2
2
inverter
1
The logical effort values are derived from the n and p-transistor sizes of the
gates, and are specified per each input. The denominator term, 3, comes from
the sum of the channel widths of the n and p-transistor which is a measure of
the gate capacitor (input capacitance). The numerator terms are the sums of the
channel widths of the respective gates.
For a more in depth discussion, please see http://www-md.e-technik.uni-rostock.de/lehre/vlsi_ii/Harris/LogicalEffort.pdf
Modern VLSI Design 3e: Chapter 4
Copyright  1998, 2002 Prentice Hall PTR
Logical effort along a path

Logical effort along a chain of gates:
– G = P gi .

Total electrical (fanout) effort along path
depends on ratio of first and last stage
capacitances:
– H = Cout/Cin.
Modern VLSI Design 3e: Chapter 4
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Branching effort
Takes into account fanout.
 Branching effort at one stage:

– b = (Conpath + Coffpath/ Conpath)

Branching effort along path:
– B = P bi.
Modern VLSI Design 3e: Chapter 4
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Path delay

Path effort:
– F = GBH.

Path delay is sum of delays of gates along
the path:
– D = S gi hi + S pi = DF + P.
Modern VLSI Design 3e: Chapter 4
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Sizing the transistors

Optimal buffer chains are exponentially
tapered:
– f^ = F 1/N.

Determine W/L of each gate on path by
working backward from the last gate:
– C in,i = gi C out,i / f^
Modern VLSI Design 3e: Chapter 4
Copyright  1998, 2002 Prentice Hall PTR
Example: logical effort

Size transistors in a chain of three two-input
NAND gates.
– First NAND is driven by minimum-size
inverter.
– Last NAND is connected to 4X inverter.
Modern VLSI Design 3e: Chapter 4
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Example, cont’d.
Logical effort G = 4/3 * 4/3 * 4/3.
 Branching effort = 1.
 Electrical effort = 4.
 F = G B H = 9.5.
 Optimum effort per stage f^ = 2.1.
 Delay = 3*2.1 = 6.3

Modern VLSI Design 3e: Chapter 4
Copyright  1998, 2002 Prentice Hall PTR