Transcript Transistors and Layout 2 - Electrical and Computer

Topics
Design rules and fabrication.
 SCMOS scalable design rules.
 Stick diagrams.

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Why we need design rules
Masks are tooling for manufacturing.
 Manufacturing processes have inherent
limitations in accuracy.
 Design rules specify geometry of masks
which will provide reasonable yields.
 Design rules are determined by experience.

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Manufacturing problems
Photoresist shrinkage, tearing.
 Variations in material deposition.
 Variations in temperature.
 Variations in oxide thickness.
 Impurities.
 Variations between lots.
 Variations across a wafer.

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Transistor problems

Variations in threshold voltage:
– oxide thickness;
– ion implantation;
– poly variations.
Changes in source/drain diffusion overlap.
 Variations in substrate.

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Wiring problems
Diffusion: changes in doping -> variations
in resistance, capacitance.
 Poly, metal: variations in height, width ->
variations in resistance, capacitance.
 Shorts and opens:

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Oxide problems
Variations in height.
 Lack of planarity -> step coverage.

metal 2
metal 2
Modern VLSI Design 3e: Chapter 2
metal 1
Copyright  1998, 2002 Prentice Hall PTR
Via problems
Via may not be cut all the way through.
 Undersize via has too much resistance.
 Via may be too large and create short.

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
MOSIS SCMOS design rules






Designed to scale across a wide range of
technologies.
Designed to support multiple vendors.
Designed for educational use.
Fairly conservative.
http://www.mosis.com/design/rules/
“The standard CMOS technology accessed by
MOSIS is a single polysilicon, double metal,
bulk CMOS process with enhancement-mode
n-MOSFET and p-MOSFET devices”.
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
 and design rules
 is the size of a minimum feature.
 Specifying  particularizes the scalable
rules.
 Parasitics are generally not specified in
units

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Wires
All wire widths are multiples of 
6
metal 3
3
metal 2
3
metal 1
3
pdiff/ndiff
2
poly
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Transistors
2
poly
3
2
diffusion
3
substrate
1
3
All measures are multiples of 
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Vias

Types of via: metal1/diff, metal1/poly,
metal1/metal2.
4
4
1
2
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Metal 3 via
Type: metal3/metal2.
 Rules:

–
–
–
–
cut: 3 x 3
overlap by metal2: 1
minimum spacing: 3
minimum spacing to via1: 2
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Tub tie
4
1
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Spacing
diffusion/diffusion: 3
 poly/poly: 2
 poly/diffusion: 1
 via/via: 2
 metal1/metal1: 3
 metal2/metal2: 4
 metal3/metal3: 4

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Overglass
Cut in passivation layer.
 Minimum bonding pad: 100 m.
 Pad overlap of glass opening: 6
 Minimum pad spacing to unrelated metal2
or metal3: 30
 Minimum pad spacing to unrelated metal1,
poly, active: 15

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Stick diagrams
A stick diagram is a cartoon of a layout.
 Does show all components/vias (except
possibly tub ties), relative placement.
 Does not show exact placement, transistor
sizes, wire lengths, wire widths, tub
boundaries.

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Stick layers
metal 3
metal 2
metal 1
poly
ndiff
pdiff
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Dynamic latch stick diagram
VDD
in
out
VSS
phi’
Modern VLSI Design 3e: Chapter 2
phi
Copyright  1998, 2002 Prentice Hall PTR
Sticks design of multiplexer

Start with NAND gate:
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
NAND sticks
VDD
a
out
b
VSS
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
One-bit mux sticks
VDD
ai
bi
a
out
N1
(NAND)
b
a
out
select
select’
a
N1
(NAND)
b
out
N1
(NAND)
b
VSS
Modern VLSI Design 3e: Chapter 2
Out =((ai&s)’ &(bi&s’)’)’Copyright  1998, 2002 Prentice Hall PTR
3-bit mux sticks
select’
a2
b2
a1
b1
ai
bi
ai
bi
select
select’
m2(one-bit-mux)
select’
select
m2(one-bit-mux)
select’
a0
b0
select
ai
bi
Modern VLSI Design 3e: Chapter 2
select
m2(one-bit-mux)
VDD
oi
VSS
o2
VDD
oi
VSS
o1
VDD
oi
VSS
o0
Copyright  1998, 2002 Prentice Hall PTR
Layout design and analysis tools
Layout editors are interactive tools.
 Design rule checkers are generally batch--identify DRC errors on the layout.
 Circuit extractors extract the netlist from the
layout.
 Connectivity verification systems (CVS)
compare extracted and original netlists.

Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Automatic layout
Cell generators (macrocell generators)
create optimized layouts for ALUs, etc.
 Standard cell/sea-of-gates layout creates
layout from predesigned cells + custom
routing.

– Sea-of-gates allows routing over the cell.
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Standard cell layout
Modern VLSI Design 3e: Chapter 2
routing area
routing area
routing area
routing area
Copyright  1998, 2002 Prentice Hall PTR
Homework Set 2
Problems 2-1,2-2,2-3, 2.10 (a),(b), pp. 103-105, Textbook,
Due, September 28, 2006.
October -1: In problem 2.10, use the side-wall capacitance as
an estimate for the overhang capacitance for a 0.5micron
process. Side-wall parasitic capacitance per micrometer is
specified for both p and n type diffusion on page 85. The
perimeter of the channel is given by 2(W+L). The bottom-wall
parasitic capacitances for p and n type diffusions are also
specified on page 85. Use the area (WL) to find the total
bottom-wall capacitance of the source/drain region. The total
capacity is found by adding the two together.
Modern VLSI Design 3e: Chapter 2
Copyright  1998, 2002 Prentice Hall PTR
Homework Set 2
October -2: The sidewall capacitance accounts for the reverse-biased pn junctions between
the source (or drain) and the substrate, and source (or drain) and the channel. Since the
thickness of the source or drain diffusion is much smaller than its length or width, the
perimeter of the diffusion is used to compute the sidewall capacitance. (For additional
discussion, please refer to p. 110, J. M. Rabaey, Digital Integrated Circuits.)
G
S
W
Modern VLSI Design 3e: Chapter 2
D
L
substrate
Copyright  1998, 2002 Prentice Hall PTR