Transcript week9

Lectures 21, 22
FPGA and Top-Down
Design Flow
Mar. 3 and 5, 2003
Modern VLSI Design 3e: Chapter 3
week9-1
Partly from 2002 Prentice Hall PTR
What is an FPGA ?
Fully SRAM
based
configuration
Block Memory.
Configurable Logic
Blocks (CLB)
— Used to form
adders,
accumulators,
multipliers, etc.
Input/Output
Blocks (IOB)
Modern VLSI Design 3e: Chapter 3
week9-2
Partly from 2002 Prentice Hall PTR
What a Range of Devices:
Which One?
 The lowest cost devices for DSP
applications ($5 to $10)
— 96 to 864 CLBs with up to 48k-bits RAM
 The father device from which all
Virtex devices have been derived
— Rarely used for new designs
— 384 to 6144 CLBs with up to 128k-bits
RAM
Cont’d on next slide
Modern VLSI Design 3e: Chapter 3
week9-3
Partly from 2002 Prentice Hall PTR
What a Range of Devices:
Which One?
 384 to 16224 CLBs with up to
832k-bits RAM
 For those particularly memory
intensive algorithms
— 2400 to 4704 CLBs with up to
1120k-bits RAM
 128 to 23,296 CLBs* with up to
3024k-bits RAM
— Latest family and most DSP-focused
FPGA architecture ever to be released
*scaled to enable comparison
Modern VLSI Design 3e: Chapter 3
week9-4
Partly from 2002 Prentice Hall PTR
Xilinx FPGA Device
Architecture
 Uniform structure of programmable blocks, which can be
connected together using programmable interconnect
Fully
programmable.
Replace all
functionality in
<50ms
Memory Blocks
Input/Output
Blocks (IOB)
Programmable Interconnect
Modern VLSI Design 3e: Chapter 3
Digital Clock
Management Blocks
(DCM)
week9-5
Configurable
Logic Blocks
(CLB)
Partly from 2002 Prentice Hall PTR
Spartan-II
 Spartan-II geared to high volume production
— Memory blocks are located
down each side of the
device
– Each memory block is 4
CLBs high
— Since the area of CLBs
increases more than the
length of the two edges, the
CLB to block memory ratio
increases with larger
devices
XC2S15 = 24 CLB per Block RAM
XC2S150 = 72 CLB per Block RAM
Modern VLSI Design 3e: Chapter 3
week9-6
Partly from 2002 Prentice Hall PTR
Contents of the Course
ASIC



FPGA
Transistor and Layout
Gate and Schematic
Systems and VHDL/Verilog
Modern VLSI Design 3e: Chapter 3
week9-7
Partly from 2002 Prentice Hall PTR
Contents of the Course (cont’d)
2 ASIC labs



Transistor/Layout
Gate and Schematic
Systems/VHDL
2 FPGA labs
(Cadence)
(Xilinx
Foundation)
(Synopsys)
Modern VLSI Design 3e: Chapter 3
week9-8
Partly from 2002 Prentice Hall PTR
Xilinx Foundation Tutorial
Lab 3: Top-down design
Lab 4: Download to FPGA development board
Modern VLSI Design 3e: Chapter 3
week9-9
Partly from 2002 Prentice Hall PTR
Lecture 23
Driving Large Load
Pass Logic
Mar. 7, 2003
Modern VLSI Design 3e: Chapter 3
week9-10
Partly from 2002 Prentice Hall PTR
Driving large loads

Sometimes, large loads must be driven:
– off-chip;
– long wires on-chip.

Sizing up the driver transistors only pushes
back the problem—driver now presents
larger capacitance to earlier stage.
Modern VLSI Design 3e: Chapter 3
week9-11
Partly from 2002 Prentice Hall PTR
Cascaded driver circuit
Modern VLSI Design 3e: Chapter 3
week9-12
Partly from 2002 Prentice Hall PTR
Optimal sizing
Use a chain of inverters, each stage has
transistors a larger than previous stage.
 Minimize total delay through driver chain:

– ttot = n(Cbig/Cg)1/n tmin.

Optimal number of stages:
– nopt = ln(Cbig/Cg).

Driver sizes are exponentially tapered with
size ratio a.
Modern VLSI Design 3e: Chapter 3
week9-13
Partly from 2002 Prentice Hall PTR
Example 1
Modern VLSI Design 3e: Chapter 3
week9-14
Partly from 2002 Prentice Hall PTR
Topics

Swtich logic.
Modern VLSI Design 3e: Chapter 3
week9-15
Partly from 2002 Prentice Hall PTR
Switch logic
Can implement Boolean formulas as
networks of switches.
 Can build switches from MOS transistors—
transmission gates.
 Transmission gates do not amplify but have
smaller layouts.

Modern VLSI Design 3e: Chapter 3
week9-16
Partly from 2002 Prentice Hall PTR
Types of switches
Modern VLSI Design 3e: Chapter 3
week9-17
Partly from 2002 Prentice Hall PTR
Behavior of n-type switch
n-type switch has source-drain voltage drop
when conducting:
– conducts logic 0 perfectly;
– introduces threshold drop into logic 1.
VDD
VDD - Vt
VDD
Modern VLSI Design 3e: Chapter 3
week9-18
Partly from 2002 Prentice Hall PTR
n-type switch driving static logic
Switch underdrives static gate, but gate
restores logic levels.
VDD
VDD - Vt
VDD
Modern VLSI Design 3e: Chapter 3
week9-19
Partly from 2002 Prentice Hall PTR
n-type switch driving switch
logic
Voltage drop causes next stage to be turned on
weakly.
VDD
VDD - Vt
VDD
Modern VLSI Design 3e: Chapter 3
week9-20
Partly from 2002 Prentice Hall PTR
Behavior of complementary
switch

Complementary switch products full-supply
voltages for both logic 0 and logic 1:
– n-type transistor conducts logic 0;
– p-type transistor conducts logic 1.
Modern VLSI Design 3e: Chapter 3
week9-21
Partly from 2002 Prentice Hall PTR
Layout characteristics
Has two source/drain areas compared to one
for inverter.
 Doesn’t have gate capacitance.

Modern VLSI Design 3e: Chapter 3
week9-22
Partly from 2002 Prentice Hall PTR
Example 2
Modern VLSI Design 3e: Chapter 3
week9-23
Partly from 2002 Prentice Hall PTR
Modern VLSI Design 3e: Chapter 3
week9-24
Partly from 2002 Prentice Hall PTR