Transcript Combinational Networks 1

Topics
Layouts for logic networks.
 Channel routing.
 Simulation.

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Standard cell layout
Layout made of small cells: gates, flipflops, etc.
 Cells are hand-designed.
 Assembly of cells is automatic:

– cells arranged in rows;
– wires routed between (and through) cells.
Modern VLSI Design 3e: Chapter 4
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Standard cell structure
pin
pullups
Feedthrough area
VDD
n tub
Intra-cell wiring
pulldowns
p tub
VSS
pin
Modern VLSI Design 3e: Chapter 4
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Standard cell design

Pitch: height of cell.
– All cells have same pitch, may have different
widths.
VDD, VSS connections are designed to run
through cells.
 A feedthrough area may allow wires to be
routed over the cell.

Modern VLSI Design 3e: Chapter 4
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Single-row layout design
cell
cell
cell
cell
cell
Routing
wire channel Horizontal track
Vertical track
cell
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cell
cell
cell
height
cell
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Routing channels

Tracks form a grid for routing.
– Spacing between tracks is center-to-center
distance between wires.
– Track spacing depends on wire layer used.

Different layers are (generally) used for
horizontal and vertical wires.
– Horizontal and vertical can be routed relatively
independently.
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Routing channel design
Placement of cells determines placement of
pins.
 Pin placement determines difficulty of
routing problem.
 Density: lower bound on number of
horizontal tracks needed to route the
channel.

– Maximum number of nets crossing from one
end of channel to the other.
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Pin placement and routing
a
Density = 3
b
c
b
c
a
before
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a
a
b
Density = 2
c
c
b
before
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Example: full adder layout

Two outputs: sum, carry.
n1
x1
n2
n4
x2
sum
n3
carry
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Layout methodology

Generate candidates, evaluate area and
speed.
– Can improve candidate without starting from
scratch.

To generate a candidate:
– place gates in a row;
– draw wires between gates and primary
inputs/outputs;
– measure channel density.
Modern VLSI Design 3e: Chapter 4
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A candidate layout
Density = 5
a
b
x1
c
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x2
n1
n2
n3
s
n4
cout
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Improvement strategies

Swap pairs of gates.
– Doesn’t help here.

Exchange larger groups of cells.
– Swapping order of sum and carry groups
doesn’t help either.

This seems to be the placement that gives
the lowest channel density.
– Cell sizes are fixed, so channel height
determines area.
Modern VLSI Design 3e: Chapter 4
Copyright  1998, 2002 Prentice Hall PTR
Left-edge algorithm
Basic channel routing algorithm.
 Assumes one horizontal segment per net.
 Sweep pins from left to right:

– assign horizontal segment to lowest available
track.
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Example
A
A
B
Modern VLSI Design 3e: Chapter 4
B
B
C
C
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Limitations of left-edge
algorithm

Some combinations of nets require more
than one horizontal segment per net.
A
B
?
B
A
aligned
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Vertical constraints

Aligned pins form vertical constraints.
– Wire to lower pin must be on lower track; wire
to upper pin must be above lower pin’s wire.
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A
B
B
A
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Dogleg wire

A dogleg wire has more than one horizontal
segment.
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A
B
B
A
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Rat’s nest plot

Can be used to judge placement before final
routing.
Modern VLSI Design 3e: Chapter 4
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Simulation

Goals of simulation:
–
–
–
–
functional verification;
timing;
power consumption;
testability.
Modern VLSI Design 3e: Chapter 4
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Types of simulation

Circuit simulation:
– analog voltages and currents.

Timing simulation:
– simple analog models to provide timing but not
detailed waveforms.

Switch simulation:
– transistors as semi-ideal switches.
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Types of simulation, cont’d.

Gate simulation:
– logic gates as primitive elements.

Models for gate simulation:
– zero delay;
– unit delay;
– variable delay.

Fault simulation:
– models fault propagation (more later).
Modern VLSI Design 3e: Chapter 4
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Example: switch simulation
+
0 c
+
d 1X
0
X
b
o
X1
a
1
0 c
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Example, cont’d.
+
0 c
+
d 01
01
b
o
01
a
10
0 c
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