Transcript Combinational Gates 2

Topics

Electrical properties of static combinational
gates:
– transfer characteristics;
– delay;
– power.
Effects of parasitics on gate.
 Driving large loads.

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Logic levels
Solid logic 0/1 defined by VSS/VDD.
 Inner bounds of logic values VL/VH are not
directly determined by circuit properties, as
in some other logic families.

VDD
logic 1
unknown
VSS
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VH
VL
logic 0
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Logic level matching

Levels at output of one gate must be
sufficient to drive next gate.
>
<
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Transfer characteristics

Transfer curve shows static input/output
relationship—hold input voltage, measure
output voltage.
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Inverter transfer curve
|slope| <1
logic 1
VDD
VIH
unknown
|slope| >1
VIL
logic 0
VSS
|slope| <1
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Logic thresholds
Choose threshold voltages at points where
slope of transfer curve = -1.
 Inverter has a high gain between VIL and
VIH points, low gain at outer regions of
transfer curve.
 Note that logic 0 and 1 regions are not equal
sized—in this case, high pullup resistance
leads to smaller logic 1 range.

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Noise margin
Noise margin = voltage difference between
output of one gate and input of next. Noise
must exceed noise margin to make second
gate produce wrong output.
 In static gates, t= voltages are VDD and
VSS, so noise margins are VDD-VIH and VILVSS.

Noise < VDD-VIH, VIL-VSS for correct operation
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Delay

Assume ideal input (step), RC load.
wire + transistor
Charge when pull-up is on,
discharge when pull-down is on.
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Delay assumptions

Assume that only one transistor is on at a time.
This gives two cases:
– rise time, pullup on;
– fall time, pullup off.

Assume resistor model for transistor. Ignores
saturation region and mischaracterizes linear
region, but results are acceptable. (In both
pull-up and pull-down cases.)
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Current through transistor

Transistor starts in saturation region, then
moves to linear region. (In both pull-up and
pull-down cases.)
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Resistive model for transistor

Average V/I at two voltages:
– maximum output voltage
– middle of linear region

Voltage is Vds, current is given Id at that
drain voltage. Step input means that Vgs =
VDD always.
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Resistive approximation
Rl
Rs
Rn= (Rs + Rl)/2
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Ways of measuring gate delay
Delay: time required for gate’s output to
reach 50% of final value.
 Transition time: time required for gate’s
output to reach 10% (logic 0) or 90% (logic
1) of final value. (fall or rise time).

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Inverter delay circuit

Load is resistor + capacitor, driver is
resistor. (Pull-down transistor is “on” case):
transistor
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transistor
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Inverter delay with t model
t model: gate delay based on RC time
constant t. (Discharging case)
 Vout(t) = VDD exp{-t/(Rn+RL)CL}= 0.5VDD
 td= 0.69(Rn+RL)CL
 tf = - (Rn+RL)CL ln 0.1/0.9 = 2.2 (Rn+RL)CL
 (Use 0.1 VDD and 0.9 VDD)
 For pullup time, use pullup resistance.

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t model inverter delay

0.5 micron process:
– Rn = 3.9 kW
– CL = 0.68 fF

So
– td = 0.69 x 3.9 x .68E-15 = 1.8 ps. (delay)
– tf = 2.2 x 3.9 x .68E-15 = 5.8 ps. (fall time)
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Quality of RC approximation
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Quality of step input
approximation
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Results of using small pullup
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Other models

Current source model (used in power/delay
studies):
– tf = CL (VDD-VSS)/Id (relies on capacitive charging
or discharging without a resistor assuming a current
source model of a transistor.)
– = CL (VDD-VSS)/0.5 k’ (W/L) (VDD-VSS -Vt)2

Fitted model: fit curve to measured circuit
characteristics.
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Body effect and gates


Difference between source and substrate voltages causes
body effect.
Source for gates in middle of network may not equal
substrate: (This causes an upward shift in the threshold (turn on) voltage of the transistor. Consequently,
transistors closer to the power supply have a higher threshold to turn on. Therefore connecting those signals that
arrive early to transistors closer to the power supply will give them more time to turn their transistors on or off and
match the arrival times of late arriving signals .)
0
0
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Source above VSS
Body effect
capacitance
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Body effect and gate input
ordering

To minimize body effect, put early arriving
signals at transistors closest to power supply:
Early arriving signal
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Power consumption analysis
Almost all power consumption comes from
switching behavior.
 Static power dissipation comes from
leakage currents.
 Surprising result: power consumption is
independent of the sizes of the pullups and
pulldowns. (Please see pp. 136-137 in
textbook.)

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Power consumption circuit

Input is square wave.
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Power consumption
A single cycle requires one charge and one
discharge of capacitor: E = CL(VDD - VSS)2 .
 Clock frequency f = 1/t.
 Energy E = CL(VDD - VSS)2.
 Power = E x f = f CL(VDD - VSS)2.
 (Energy per unit time)

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Observations on power
consumption
Resistance of pullup/pulldown drops out of
energy calculation.
 Power consumption depends on operating
frequency.

– Slower-running circuits use less power (but not
less energy to perform the same computation).
(They take longer to charge but store or remove
the same amount of energy into (from) the load
capacitor.)
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Speed-power product



Also known as power-delay product.
Helps measure quality of a logic family.
For static CMOS:
– SP = P/f = CV2.

Static CMOS speed-power product is independent
of operating frequency.
– Voltage scaling depends on this fact. (Power reduces
quadratically with voltage whereas delay reduces
linearly with it.)
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Parasitics and performance
a
b
c
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Effect of parasitics

a: Capacitance on power supply is not bad, can be good in absence of
inductance. Resistance slows down static gates, may cause pseudonMOS circuits to fail. (Adding a capacitance between the power supply and the
pull-up transistor will reduce the total capacitive load on the next stage when charging
it, and will thus decrease its charge time. Adding a resistance will increase the resistive
load requiring longer time to charge since more current will dissipate through the
increased resistance)
+
C1
C2
Ceff = C1C2/ (C1 + C2) < C1, C2
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Effects of parasitics, cont’d
b: Increasing capacitance/resistance reduces input slope.
 c: Similar to parasitics at b, but resistance near source is

more damaging, since it must charge more capacitance. (It
will take longer for CL to charge because, Cx must be
charged first.)
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Driving large loads

Sometimes, large loads must be driven:
– off-chip;
– long wires on-chip.

Sizing up the driver transistors only pushes
back the problem—driver now presents
larger capacitance to earlier stage.
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Cascaded driver circuit
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Optimal sizing


Use a chain of inverters, each stage has transistors a larger
than previous stage.
Minimize total delay through driver chain:
– ttot = n(Cbig/Cg)1/n tmin.

Optimal number of stages:
– nopt = ln(Cbig/Cg).

Driver sizes are exponentially tapered with size ratio a.
(The total time is minimized when a = e. Thus, 2 to 3
stages give the minimum total delay when cascading two
or more gates.)
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