Transcript Logic

MICROELETTRONICA
Combinational circuits
Lection 6
1
Outline
•
•
•
•
•
•
•
Bubble Pushing
Compound Gates
Logical Effort Example
Input Ordering
Asymmetric Gates
Skewed Gates
Best P/N ratio
2
Bubble Pushing
• Start with network of AND / OR gates
• Convert to NAND / NOR + inverters
• Push bubbles around to simplify logic
– Remember DeMorgan’s Law
Y
Y
(a)
(b)
Y
(c)
D
Y
(d)
3
Example
• Sketch a design using one compound gate and one NOT gate.
Assume ~S is available
D0
S
D1
S
Y
4
Compound Gates
• Logical Effort of compound gates
unit inverter
AOI21
YA
Y  A BC
Y  A BC D
A
B
C
A
B
C
D
A
Y
A
A
2
1
Y
AOI22
Y
4 B
C
A
2
B
2
4
4
C
Y
1
Complex AOI
Y
A
4 B
4
C
4 D
4
A
2 C
2
B
2 D
2
Y
Y  A B  C  D E
D
E
A
B
C
Y
B
6
C
6
A
3
D
6
E
6
E
2
A
2
D
2
2
C
B
gA = 3/3
gA = 6/3
gA = 6/3
gA = 5/3
p = 3/3
gB = 6/3
gB = 6/3
gB = 8/3
gC = 5/3
gC = 6/3
gC = 8/3
p = 7/3
gD = 6/3
gD = 8/3
p = 12/3
gE = 8/3
Y
2
p = 16/3
5
MUX Example
• The multiplexer has a maximum input capacitance of 16
units on each input. It must drive a load of 160 units.
Estimate the delay of the NAND and compound gate
designs.
D0
S
Y
D1
S
D0
S
D1
S
Y
H = 160 / 16 = 10
B=1
N=2
6
NAND Solution
P 224
G  (4 / 3) (4 / 3)  16 / 9
F  GBH  160 / 9
fˆ  N F  4.2
D0
S
Y
D1
S
D  Nfˆ  P  12.4
7
Compound Solution
P  4 1  5
G  (6 / 3) (1)  2
F  GBH  20
fˆ  N F  4.5
D0
S
D1
S
Y
D  Nfˆ  P  14
8
Input Order
• Our parasitic delay model was too
simple
– Calculate parasitic delay for Y falling
• If A arrives latest? 2
• If B arrives latest? 2.33
2
2
A
2
B
2x
Y
6C
2C
9
Inner & Outer Inputs
• Outer input is closest to rail (B)
• Inner input is closest to output (A)
2
2
A
2
B
2
• If input arrival time is known
– Connect latest input to inner terminal
Y
10
Asymmetric Gates
Asymmetric gates favor one input over another
Ex: suppose input A of a NAND gate is most critical
Use smaller transistor on A (less capacitance)
Boost size of noncritical input A
Y
reset
So total resistance is same
2
2
Y
gA = 10/9
A
4/3
gB = 2
4
reset
gtotal = gA + gB = 28/9
Asymmetric gate approaches g = 1 on critical input
But total logical effort goes up
11
Skewed Gates
Skewed gates favor one transition over another
Ex: suppose rising output of inverter is most critical
Downsize noncritical nMOS transistor
HI-skew
inverter
unskewed inverter
(equal rise resistance)
2
A
2
Y
1/2
unskewed inverter
(equal fall resistance)
A
1
Y
1
A
Y
1/2
Calculate logical effort by comparing to unskewed
inverter with same effective resistance on that edge.
gu = 2.5 / 3 = 5/6
gd = 2.5 / 1.5 = 5/3
12
HI- and LO-Skew
Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that
gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.
Skewed gates reduce size of noncritical transistors
HI-skew gates favor rising output (small nMOS)
LO-skew gates favor falling output (small pMOS)
Logical effort is smaller for favored direction but
larger for the other direction
13
Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
1
Y
gu = 1
gd = 1
gavg = 1
A
2
B
2
2
HI-skew
Y
1/2 g = 5/6
u
gd = 5/3
gavg = 5/4
1
B
1
1
LO-skew
1
Y
gu = 4/3
gd = 2/3
gavg = 1
2
B
2
4
1
1
B
4
A
4
1/2
gu = 1
gd = 2
gavg = 3/2
1
A
A
gu = 5/3
gd = 5/3
gavg = 5/3
Y
Y
1
A
4
gu = 4/3
gd = 4/3
gavg = 4/3
2
A
B
Y
Y
2
A
2
Y
2
A
NOR2
1/2
B
2
A
2
gu = 3/2
gd = 3
gavg = 9/4
Y
gu = 2
gd = 1
gavg = 3/2
1
1
gu = 2
gd = 1
gavg = 3/2
14
Asymmetric Skew
• Combine asymmetric and skewed gates
– Downsize noncritical transistor or unimportant
input
– Reduces parasitic delay for critical input
A
reset
Y
1
A
reset
2
Y
4/3
4
15
Best P/N Ratio
• We have selected P/N ratio for unit rise and fall
resistance (m = 2-3 for an inverter).
• Alternative: choose ratio for least average delay
• Ex: inverter
–
–
–
–
–
–
Delay driving identical inverter
A
tpdf = (P+1)
tpdr = (P+1)(m/P)
tpd = (P+1)(1+m/P)/2 = (P + 1 + m + m/P)/2
Differentiate tpd w.r.t. P
Least delay for P = m
P
1
16
P/N Ratios
• In general, best P/N ratio is sqrt of equal delay ratio.
– Only increases average delay slightly for inverters
– But significantly decreases area and power
Inverter
NAND2
2
fastest
P/N ratio
A
1.414
Y
1
gu = 1.15
gd = 0.81
gavg = 0.98
NOR2
2
Y
A
2
B
2
B
2
A
2
Y
gu = 4/3
gd = 4/3
gavg = 4/3
1
1
gu = 2
gd = 1
gavg = 3/2
17
Observations
• For speed:
– NAND vs. NOR
– Many simple stages vs. fewer high fan-in
stages
– Latest-arriving input
• For area and power:
– Many simple stages vs. fewer high fan-in
stages
18
Logic families - Outline
• Pseudo-nMOS Logic
• Dynamic Logic
• Pass Transistor Logic
19
Introduction
• What makes a circuit fast?
–
–
–
–
I = C dV/dt -> tpd  (C/I) DV
low capacitance
high current
small swing
• Logical effort is proportional to C/I
• pMOS are the enemy!
– High capacitance for a given current
• Can we take the pMOS capacitance off the
input?
• Various circuit families try to do this…
20
Pseudo-nMOS
• In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON
• In CMOS, use a pMOS that is always ON
– Ratio issue
– Make pMOS about ¼ effective strength of pulldown network
1.8
1.5
load
P/2
1.2
P = 24
Ids
Vout 0.9
Vout
16/2
Vin
0.6
P = 14
0.3
P=4
0
0
0.3
0.6
0.9
1.2
1.5
1.8
Vin
21
Pseudo-nMOS Gates
• Design for unit current on output
to compare with unit inverter.
• pMOS fights nMOS
Inverter
2/3
Y
A
4/3
Y
inputs
f
NAND2
gu
gd
gavg
pu
pd
pavg
= 4/3
= 4/9
= 8/9
= 6/3
= 6/9
= 12/9
A
B
gu
2/3
g
Y gd
avg
8/3
pu
pd
8/3
pavg
NOR2
= 8/3
= 8/9
= 16/9
= 10/3
= 10/9
= 20/9
2/3
A
4/3 B
gu
gd
gavg
Y pu
4/3 pd
pavg
= 4/3
= 4/9
= 8/9
= 10/3
= 10/9
= 20/9
22
Pseudo-nMOS Design
• Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
Pseudo-nMOS
•
•
•
•
•
G = 1 * 8/9 = 8/9
F = GBH = 8H/9
P = 1 + (4+8k)/9 = (8k+13)/9
N=2
4 2 H 8k  13
1/N

D = NF + P =
3
9
In1
1
Ink
1
Y
H
23
Pseudo-nMOS Power
• Pseudo-nMOS draws power whenever Y = 0
– Called static power P = I•VDD
– A few mA / gate * 1M gates would be a problem
– This is why nMOS went extinct!
• Use pseudo-nMOS sparingly for wide NORs
• Turn off pMOS when not in use
en
Y
A
B
C
24
Dynamic Logic
• Dynamic gates uses a clocked pMOS pullup
• Two modes: precharge and evaluate
2
A

2/3
Y
1
Y
1
A
Static
4/3
Pseudo-nMOS

Precharge
Y
A
1
Dynamic
Evaluate
Precharge
Y
25
FOOT
• What if pulldown network is ON during precharge?
• Use series evaluation transistor to prevent fight.
precharge transistor

Y


Y
inputs
A
Y
inputs
f
f
foot
footed
unfooted
26
Logical Effort
Inverter

unfooted
NAND2
1
gd
pd

footed
2
B
2
gd
pd

1
A
3
2
gd
pd
= 2/3
= 3/3
B
3
3

1
1
B
Y
= 2/3
= 3/3
A
Y
1
2
A
= 1/3
= 2/3
Y
A
1
Y
1
Y
A

NOR2

1
gd
pd
= 1/3
= 3/3
1
Y
gd
pd
= 3/3
= 4/3
A
2
B
2
2
gd
pd
= 2/3
= 5/3
27
Monotonicity
• Dynamic gates require monotonically rising inputs during
evaluation

– 0 -> 0
Y
A
– 0 -> 1
– 1 -> 1
violates monotonicity
during evaluation
– But not 1 -> 0
A

Precharge
Evaluate
Precharge
Y
Output should rise but does not
28
Monotonicity problems
• But dynamic gates produce monotonically falling outputs during
evaluation
• Illegal for one dynamic gate to drive another!
A=1

A
Y

Precharge
Evaluate
Precharge
X
X
X monotonically falls during evaluation
Y
Y should rise but cannot
29
Domino Gates
• Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs

domino AND
W
Precharge
Evaluate
Precharge
W
X
Y
Z
X
A
B
C

Y
Z
dynamic static
NAND inverter

A
B


W
X
H
C
Y
H
Z
=
A
B

X
C
Z
30
Domino Optimizations
• Each domino gate triggers next one, like a string of dominos
toppling over
• Gates evaluate sequentially but precharge in parallel
• Thus evaluation is more critical than precharge
• HI-skewed static stages can perform logic

S0
S1
S2
S3
D0
D1
D2
D3
H
Y

S4
S5
S6
S7
D4
D5
D6
D7
31
Dual-Rail Domino
•
•
Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR
Dual-rail domino solves this problem
Takes true and complementary inputs
Produces true and complementary outputs
Sig_h
Sig_l
Meaning
0
0
Precharged

Y_l
0
1
“0”
1
0
“1”
1
1
Not allowed
inputs
f
Y_h
f

32
Example: AND/NAND
• Given A_h, A_l, B_h, B_l
• Compute Y_h = A * B, Y_l = ~(A * B)
• Pulldown networks are conduction complements

Y_l
A_h
= A*B
A_l
B_l
Y_h
= A*B
B_h

33
Example: XOR/XNOR
• Sometimes possible to share transistors

Y_l
= A xnor B
A_h
Y_h
A_l
A_l
B_l
B_h
A_h
= A xor B

34
Leakage
• Dynamic node floats high during evaluation
– Transistors are leaky (IOFF  0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper

A
1 k
X
H
Y
2
2
35
Charge Sharing
• Dynamic gates suffer from charge sharing


A
B=0
Y
CY
x
Cx
A
Y
Charge sharing noise
x
CY
Vx  VY 
VDD
C x  CY
36
Secondary Precharge
• Solution: add secondary precharge transistors
– Typically need to precharge every other node
• Big load capacitance CY helps as well

Y
A
secondary
precharge
transistor
x
B
37
Noise Sensitivity
• Dynamic gates are very sensitive to noise
– Inputs: VIH  Vtn
– Outputs: floating output susceptible noise
• Noise sources
– Capacitive crosstalk
– Charge sharing
– Power supply noise
– Feedthrough noise
– And more!
38
Domino Summary
• Domino logic is attractive for high-speed circuits
– 1.5 – 2x faster than static CMOS
– But many challenges:
• Monotonicity
• Leakage
• Charge sharing
• Noise
• Widely used in high-performance microprocessors
39
Pass Transistor Circuits
• Use pass transistors like switches to do logic
• Inputs drive diffusion terminals as well as gates
• CMOS + Transmission Gates:
– 2-input multiplexer
– Gates should be restoring
S
S
A
A
S
S
Y
Y
B
B
S
S
40
LEAP
• LEAn integration with Pass transistors
• Get rid of pMOS transistors
– Use weak pMOS feedback to pull fully high
– Ratio constraint
S
A
S
L
Y
B
41
CPL
• Complementary Pass-transistor Logic
– Dual-rail form of pass transistor logic
– Avoids need for ratioed feedback
– Optional cross-coupling for rail-to-rail swing
S
A
S
L
Y
L
Y
B
S
A
S
B
42