Transcript EE 447 VLSI Design

EE 447
VLSI Design
Lecture 8:
Circuit Families
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Outline
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Pseudo-nMOS Logic
Dynamic Logic
Pass Transistor Logic
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Introduction
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What makes a circuit fast?
 I = C dV/dt
-> tpd  (C/I) DV
 low capacitance
 high current
B
 small swing
A
Logical effort is proportional to C/I
1
pMOS are the enemy!
 High capacitance for a given current
Can we take the pMOS capacitance off the input?
Various circuit families try to do this…
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4
Y
1
3
Pseudo-nMOS
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In the old days, nMOS processes had no pMOS
 Instead, use pull-up transistor that is always ON
In CMOS, use a pMOS that is always ON
 Ratio issue
 Make pMOS about ¼ effective strength of pulldown
network
load
1.8
1.5
P/2
1.2
Ids
P = 24
Vout
16/2
Vin
Vout 0.9
0.6
P = 14
0.3
P=4
0
0
0.3
0.6
0.9
1.2
1.5
1.8
Vin
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Pseudo-nMOS Gates
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Design for unit current on output
to compare with unit inverter.
pMOS fights nMOS
Inverter
Y
A
Y
inputs
f
NAND2
gu
gd
gavg
pu
pd
pavg
=
=
=
=
=
=
A
B
gu
g
Y gd
avg
pu
pd
pavg
NOR2
=
=
=
=
=
=
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A
B
gu
gd
gavg
Y pu
pd
pavg
=
=
=
=
=
=
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Pseudo-nMOS Gates
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Design for unit current on output
to compare with unit inverter.
pMOS fights nMOS
Inverter
2/3
Y
A
4/3
Y
inputs
f
NAND2
gu
gd
gavg
pu
pd
pavg
=
=
=
=
=
=
gu
g
Y gd
avg
8/3
pu
pd
8/3
pavg
2/3
A
B
NOR2
=
=
=
=
=
=
EE 447 VLSI Design
2/3
A
4/3 B
gu
gd
gavg
Y pu
4/3 pd
pavg
=
=
=
=
=
=
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Pseudo-nMOS Gates
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Design for unit current on output
to compare with unit inverter.
pMOS fights nMOS
Inverter
2/3
Y
A
4/3
Y
inputs
f
NAND2
gu
gd
gavg
pu
pd
pavg
= 4/3
= 4/9
= 8/9
=
=
=
A
B
gu
2/3
g
Y gd
avg
8/3
pu
pd
8/3
pavg
NOR2
= 8/3
= 8/9
= 16/9
=
=
=
EE 447 VLSI Design
2/3
A
4/3 B
gu
gd
gavg
Y pu
4/3 pd
pavg
= 4/3
= 4/9
= 8/9
=
=
=
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Pseudo-nMOS Gates
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Design for unit current on output
to compare with unit inverter.
pMOS fights nMOS
Inverter
2/3
Y
A
4/3
Y
inputs
f
NAND2
gu
gd
gavg
pu
pd
pavg
= 4/3
= 4/9
= 8/9
= 6/3
= 6/9
= 12/9
gu
g
Y gd
avg
8/3
pu
pd
8/3
pavg
2/3
A
B
NOR2
= 8/3
= 8/9
= 16/9
= 10/3
= 10/9
= 20/9
EE 447 VLSI Design
2/3
A
4/3 B
gu
gd
gavg
Y pu
4/3 pd
pavg
= 4/3
= 4/9
= 8/9
= 10/3
= 10/9
= 20/9
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Pseudo-nMOS Design
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Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
Pseudo-nMOS
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G=
F=
P=
N=
D=
In1
1
Ink
1
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H
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Pseudo-nMOS Design
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Ex: Design a k-input AND gate using pseudo-nMOS.
Estimate the delay driving a fanout of H
Pseudo-nMOS
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G = 1 * 8/9 = 8/9
F = GBH = 8H/9
P = 1 + (4+8k)/9 = (8k+13)/9
N=2
4 2 H 8k  13

D = NF1/N + P =
3
9
In1
1
Ink
1
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H
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Pseudo-nMOS Power
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Pseudo-nMOS draws power whenever Y = 0
 Called static power
P = I•VDD
 A few mA / gate * 1M gates would be a problem
 This is why nMOS went extinct!
Use pseudo-nMOS sparingly for wide NORs
Turn off pMOS when not in use
en
Y
A
B
C
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Dynamic Logic
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Dynamic gates uses a clocked pMOS pullup
Two modes: precharge and evaluate
2
A
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2/3
Y
1
Y
1
A
Static
4/3
Pseudo-nMOS
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Precharge
Y
A
1
Dynamic
Evaluate
Precharge
Y
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The Foot
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What if pulldown network is ON during precharge?
Use series evaluation transistor to prevent fight.
precharge transistor
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Y
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Y
inputs
A
Y
inputs
f
f
foot
footed
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unfooted
13
Logical Effort
Inverter

unfooted
NAND2
1
gd
pd
footed
2
2
2
B
2
gd
pd
=
=

1
1
B
Y
gd
pd
=
=
A
1
gd
pd
=
=
1
Y
1
Y
A
A
=
=
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1
Y
1
Y
A

NOR2
A
3
B
3
3

1
Y
gd
pd
=
=
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2
B
2
2
gd
pd
=
=
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Logical Effort
Inverter
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unfooted
NAND2
1
gd
pd
footed
2
2
2
B
2
gd
pd
= 2/3
= 3/3

1
1
B
Y
gd
pd
= 2/3
= 3/3
A
1
gd
pd
= 1/3
= 3/3
1
Y
1
Y
A
A
= 1/3
= 2/3
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1
Y
1
Y
A
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NOR2
A
3
B
3
3

1
Y
gd
pd
= 3/3
= 4/3
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2
B
2
2
gd
pd
= 2/3
= 5/3
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Monotonicity
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Dynamic gates require monotonically rising inputs during
evaluation
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 0 -> 0
A
 0 -> 1
 1 -> 1
violates monotonicity
during evaluation
 But not 1 -> 0
A
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Precharge
Evaluate
Precharge
Y
Output should rise but does not
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Monotonicity Woes
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But dynamic gates produce monotonically falling outputs
during evaluation
Illegal for one dynamic gate to drive another!
A=1
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A
Y
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Precharge
Evaluate
Precharge
X
X
Y
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Monotonicity Woes
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But dynamic gates produce monotonically falling outputs
during evaluation
Illegal for one dynamic gate to drive another!
A=1
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A
Y
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Precharge
Evaluate
Precharge
X
X
X monotonically falls during evaluation
Y
Y should rise but cannot
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Domino Gates
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Follow dynamic stage with inverting static gate
 Dynamic / static pair is called domino gate
 Produces monotonic outputs
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Precharge
Evaluate
Precharge
domino AND
W
W
X
Y
Z
X
A
B
C

Y
Z
dynamic static
NAND inverter

A
B
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
W
X
H
C
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H
Z
=
A
B

X
C
Z
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Domino Optimizations
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Each domino gate triggers next one, like a string of
dominos toppling over
Gates evaluate sequentially but precharge in parallel
Thus evaluation is more critical than precharge
HI-skewed static stages can perform logic
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S0
S1
S2
S3
D0
D1
D2
D3
H
Y

S4
S5
S6
S7
D4
D5
D6
D7
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Dual-Rail Domino
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Domino only performs noninverting functions:
 AND, OR but not NAND, NOR, or XOR
Dual-rail domino solves this problem
 Takes true and complementary inputs
 Produces true and complementary outputs
sig_h
0
0
1
1
sig_l
0
1
0
1
Meaning
Y_l
Prechar
inputs
ged
‘0’
‘1’
EE 447 VLSI Design
invalid
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f
Y_h
f
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Example: AND/NAND
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Given A_h, A_l, B_h, B_l
Compute Y_h = A * B, Y_l = ~(A * B)
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Example: AND/NAND
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Given A_h, A_l, B_h, B_l
Compute Y_h = A * B, Y_l = ~(A * B)
Pulldown networks are conduction complements
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Y_l
A_h
= A*B
A_l
B_l
Y_h
= A*B
B_h

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Example: XOR/XNOR
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Sometimes possible to share transistors
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Y_l
= A xnor B
A_h
Y_h
A_l
A_l
B_l
B_h
A_h
= A xor B

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Leakage
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Dynamic node floats high during evaluation
 Transistors are leaky (IOFF  0)
 Dynamic value will leak away over time
 Formerly miliseconds, now nanoseconds!
Use keeper to hold dynamic node
 Must be weak enough not to fight evaluation
weak keeper

A
1 k
X
H
Y
2
2
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Charge Sharing
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Dynamic gates suffer from charge sharing
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
A
Y
CY
x
A
Y
B=0
Cx
x
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Charge Sharing
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Dynamic gates suffer from charge sharing
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A
Y
CY
x
A
Y
B=0
Cx
Charge sharing noise
x
Vx  VY 
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Charge Sharing
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Dynamic gates suffer from charge sharing
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A
Y
CY
x
A
Y
B=0
Cx
Charge sharing noise
x
CY
Vx  VY 
VDD
C x  CY
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Secondary Precharge
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Solution: add secondary precharge transistors
 Typically need to precharge every other node
Big load capacitance CY helps as well

Y
A
secondary
precharge
transistor
x
B
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Noise Sensitivity
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Dynamic gates are very sensitive to noise
 Inputs: VIH  Vtn
 Outputs: floating output susceptible noise
Noise sources
 Capacitive crosstalk
 Charge sharing
 Power supply noise
 Feedthrough noise
 And more!
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Domino Summary
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Domino logic is attractive for high-speed circuits
 1.5 – 2x faster than static CMOS
 But many challenges:
 Monotonicity
 Leakage
 Charge sharing
 Noise
Widely used in high-performance microprocessors
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Pass Transistor Circuits
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Use pass transistors like switches to do logic
Inputs drive diffusion terminals as well as gates
CMOS + Transmission Gates:
 2-input multiplexer
 Gates should be restoring
S
S
A
A
S
S
Y
Y
B
B
S
S
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LEAP
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LEAn integration with Pass transistors
Get rid of pMOS transistors
 Use weak pMOS feedback to pull fully high
 Ratio constraint
S
A
S
L
Y
B
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CPL
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Complementary Pass-transistor Logic
 Dual-rail form of pass transistor logic
 Avoids need for ratioed feedback
 Optional cross-coupling for rail-to-rail swing
S
A
S
L
Y
L
Y
B
S
A
S
B
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