Transcript W10_Slides

Interconnect/Via
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Delay of Devices and Interconnect
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Reduction of the feature size
Increase in the influence of
the interconnect delay on
system performance
Skew
The difference in the arrival times of the clock signal to all
registers in a synchronous digital system
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An Example , The Clock Distribution Network (CDN)
A set of interconnections that delivers reliably a time
reference, clock signal , to every register element in a
synchronous digital system.
PowerPC microprocessor
32,000 master/slave latch
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Power Consumption &Routing
and system complexity
P= CV2f
Short-Circuit
Leakage
Global Interconnect
6%
6%
11% I/O
12% Clock
8%
3%
Memory
54%
Logic and Local Routing
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Delay model of the CDN, Elmore Delay
model
er0
It takes into account the interconnect resistance
and capacitance and the capacitance of the
registers
ec0//2
ec0//2
r1
s0
s1
s1
s2
r2
s0
r3
s2
r1
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r2
r3
r4
r4
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Example: Routing delay problems
The Clock Skew
In
TPD(min)
Ri
The difference between time
arrivals of the clock signal to all
the registers in a synchronous
digital system
Rj Out
/TPD(max)
Ti
Tj
S(ij) = Ti - Tj
Two conditions:
S(ij)  THOLDj - TPD(min)
S(ij)  Tclk - TPD(max)
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Race
Conditions
Permissible
range
S(ij)min
Clock Period
Limitations
S(ij)max
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Minimizing the effects of delay, The H_Tree
If it is possible to divide
the set of registers R
into two symmetric sets
recursively and
alternatively by vertical
and horizontal lines,
then the set R can be
connected by an H-tree
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Interconnect Length
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Interconnect/Via
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Cross Section View of Capacitances in
interconnect
Units are in Angstrom,
1A=0.1nm
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Interconnect
Interconnects in chips are routed in several
layers horizontally and vertically and used
according to their application
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Small line length: transistor speed governs the circuit speed.
Medium line length Transistor output resistance and
line capacitance govern the circuit speed.
Long line length, line resistance and line capacitance govern
the circuit speed.
Cooling the room temperature to 77K reduces the
resistivity by an order of magnitude.
At higher frequencies, Ghz and above the skin effect has to
be taken into account.
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Interconnect usage
Local interconnect are used for short distances on the
chip. Mainly to connect the device Drain, source, gates
or immediate devices.
Semi_global interconnect is used to connect gates FFs
other small devices within a block of the hierarchy.
Global wiring is used for long interconnect such as
Clock signal or other control signals.
Separating the interconnect wires and the devices from
each other are the
dielectric material. The dielectric material gets thicker
as move higher in the hierarchy of the wire placement
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Parallel and fringing Capacitance
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Fringing Capacitance
http://maxwell.ucdavis.edu/~electro/dc_circuits/capacit
ance.html
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Fringing Capacitance
T is the thickness of wire
H is the distance of wire to
substrate.
CF   r *

2H
T
ln( 1 
(1  1  ))
T
H
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
T
4H
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Cross Talk
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Cross talk
Is a disturbance caused by the electric or magnetic
fields of one telecommunication signal affecting a signal in
an adjacent circuit.
Two effects:
increased capacitance on the driver.
Introduction of unwanted signal or noise from one line to the
other.
Design tips:
Methods to reduce cross talk,
Increase inter_wire spacing.
Place Vdd or ground wires between signal lines.
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Fringing/ Parallel Plate Capacitance of Interconnect
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
Modeling Interconnect
LUMPED MODEL
T-MODEL
 -MODEL
2T-MODEL
2π -MODEL
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Modeling of Interconnect
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Delay of Interconnect
 delay
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rcl 2

2
 delay
rc
 N ( N  1)
2
Capacitance = C/unit area * L (length) * W (width) = C
Resistance = R/ * number of squares = R
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Delay comparison
Voltage Range
0 – 50%
0 – 63%
10 – 90%
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Lumped RC
0.69RC
RC
2.2RC
Distributed RC
0.38RC
0.5RC
0.9RC
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RC delay with distributed parameters:
• More accurate than lumped RC model
• More difficult to solve for large N
• Need full-scale SPICE simulation
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Example
A signal is propagated on a 6mm length metal 1
(M1) interconnect of CMOSIS5 Process, using
minimum wire width.
Calculate the delay and comment on methods for
reducing this delay.
6mm
Now the resistance and capacitance of CMOSIS5 are given as (from the manual):
r = 0.07 W /
2
c = 46 aF/µm , c = 46*1 exp -18, (a = 1 exp -18),
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Rent’s rule, relates number of i/O pins
T, to the number of gates N in a random
logic network:
T
T=kN**p
Where:
k = average I/O per gate
P= Rent’s exponent. It reflects wiring
complexity , p=1 is the highest.
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What is the maximum size of silicon chip?
•Power dissipation
•Packaging
•Number of pins
•Technology
•The interconnect
used
Achip  0.16
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RoCo
ln(
RintCint
CINT
Area packaging
 Cl
2
)
Co
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Thank you !
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Inductances
For die wires

4h
L
ln( )
2
d
h is the height of the wire above the substrate,
d is the diameter of the wire
 is the magnetic permeability of the material
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Inductance
For on-chip,

8h w
L
ln(  )
2
w 4h
h is the height of the wire above the substrate,
d is the diameter of the wire
 is the magnetic permeability of the material
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Ground Bounce and Vdd Sag examples from
Alterahttp://www.altera.com/literature/wp/wp_grndbnce.pdf
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Example on VDD Bounce
Determine the values of
x, y due to inductive and resistive losses
when the output driver sources 10mA in 1.5ns in the following circuit.
Assume inductance of 13.9nH/mm.
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Board Vdd
Circuit Vdd
Board Gnd
Circuit Gnd
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Example on Power lines
What will be the power line width
if you drive a 10pF load at 1GHz
Assume Vdd=3.5V.
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Example on Charge Sharing
Calculate the drop in voltage for 64 read lines each consisting of 0.1pF capacitances.
Assume bus capacitance to be 10pF.
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Thank you !
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