Transcript Copy of W12_Slides

OUTPUT Pad and Driver
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CLOCK DRIVER
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Buffering
S = scaling or tapering factor
CL = SN+1 Cg ………………
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All inverters have identical delay of
to = delay of the first stage (load =Cd+Cg)
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Buffering
If the diffusion capacitance Cd is neglected,
S = e = 2.7
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S
4
3
0
1
2
3
Cd/Cg
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Layout of Large Device
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Large Transistor Layout
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Output Drivers
Standard CMOS Driver
Open Drain/Source Driver: Single Transistors
Tri-state Driver
Bi-directional Circuit
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Tri-state Driver
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


Tri-state or High impedance
Used to drive internal or external busses
Two inputs:
Data In and Enable
Various signal assertions
En
Two types:
In
C2MOS
En
CMOS with Control Logic
VDD
Out
C2MOS
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Tri-state Driver
VDD
Control logic could be
modified to obtain
En
Inversion/non-inversion
Active low/high Enable
Out
For large load, pre-drivers
are required
PAD
En
In
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Latch-up: Trigger
Factors which trigger latch-up


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
transmission line reflections or ringing
voltage drop on the VDD bus
“hot plug in” of unpowered circuit board
electrostatic discharge
sudden transient on power and ground busses
leakage current across the junction
radiation: x-ray, cosmic
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Input PAD
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Protection Circuitry Principles
Punch Through
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Avalanche
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Protection Circuitry
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Protection Circuitry
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Input protection
Electrostatic
discharge can take place through transfer of charges from the
human body to the device.
Human body can carry up to 8000V.
Discharge can happen within hundreds of nanoseconds.
Critical field for SiO2 is about 7X106 V/cm.
For 0.5u CMOS process the gate oxide can withstand around 8V
Some protection technique is required with minimum impact on
performance
1.5K
1M
Vesd
DUT
100pF
Human Body model
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15
ESD Structures
Basic technique is to include series resistance and two clamping
diodes.
The resistance R is to limit the current and to slow down the high
voltage transitions.
R could be polysilicon or diffusion resistance
Diffusion resistance could be part of the diode structure
Typical values of R: 500 to 1k
VDD
R
PAD
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Layout of ESD Structure
This structure
uses transistors as
clamping diodes
PAD
n+
p+
Guard Ring
Guard Ring
p+
p+
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n+
n+
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Layout of ESD Structure
VDD
PAD
n+
p+
Guard Ring
Guard Ring
p+
p+
n+
n+
GND
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Another ESD Structure
VDD
PAD
R1
R2
Thick FOX
MOS Transistor
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Bi-direct PAD
VDD
Pre-drivers
IN
EN
ESD Protection Input Buffer
Control
Logic
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PAD
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Thank you !
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