Transcript [Sample Course Title Slide Insert Presentation Title]

How Do I Plan to Power
My FPGA?
FPGA and ASIC Technology
Comparison - 1
© 2009 Xilinx, Inc. All Rights Reserved
Objectives
After completing this module, you will be able to:
 Explain how static power is different from dynamic power
 Describe the impact a smaller device geometry has on static power
consumption
 Define the relationship between leakage current and junction temperature
 Describe some of the device data sheet information that pertains to power
consumption
FPGA and ASIC Technology
Comparison - 2
© 2009
2007 Xilinx, Inc. All Rights Reserved
Total Power = Static + Dynamic
 Once the device has powered up, there are two main components to
power consumption
 Static power
gate
• Primarily transistor leakage current
source
– Source to Drain leakage IS →D
– Gate to substrate leakage IGATE
• Some current from special circuits (DCM, etc)
IGATE
ISD
drain
 Dynamic power
• Switching in the FPGA core and I/O
• Determined by CV2f
– node capacitance,
– supply voltage
– switching frequency
FPGA and ASIC Technology
Comparison - 3
© 2009
2007 Xilinx, Inc. All Rights Reserved
Buf
Buf
C
The Industry Trend in Leakage Current
 New Technologies  Smaller transistor
length Higher IS →D
 Faster transistors (lower Vt ) Smaller
Gate Oxide thickness  Higher (IGATE)
 The total leakage for all transistors in the
device
– ICCINTQ = IS →D + IGATE
 Even when the device is not doing a task it
still draws some power
– This leads to the development of new
features such as Suspend and Hibernate
mode
 Smaller process geometries lead to
higher static power
FPGA and ASIC Technology
Comparison - 4
Ileakage (nA/um)
1000
100
10
Transistor Ileakage
Trend
Low
VT
1
Regular VT
0.1
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2007 Xilinx, Inc. All Rights Reserved
220 180 150 130 90
Technology Node
75
65
Properties of Leakage Current
Leakage
Current
Junction
Temperature
(TJ °C)
Normalized
ICCINTQ Typical
25
1.00
50
1.46
85
2.50
100
3.14
ICCINTQ
100 °C
85 °C
50 °C
25 °C
-40
-20
0
20
40
60
80
100
120
140
Junction Temp
°C
 Leakage current increases dramatically with Junction Temperature
FPGA and ASIC Technology
Comparison - 5
© 2009
2007 Xilinx, Inc. All Rights Reserved
Data Sheet Specifications
 Iccintq, Iccoq, Iccauxq
– These are the bare minimum currents (quiescent) required for your power
supply to operate the device
–
–
Does not guarantee that your design is going to work, just that this is the
minimum current
– Dynamic power requirements will increase the required current during
operation
Refer to the Spartan-6 FPGA Data Sheet or the Virtex-6 FPGA Data Sheet
FPGA and ASIC Technology
Comparison - 6
© 2009
2007 Xilinx, Inc. All Rights Reserved
Data Sheet Specifications
 Power-On requrements are greater than the operating current
requirements
– These are the bare minimum currents (quiescent) required for your power
supply to power up the device
–
–
–
This is used for picking out a sufficient power supply
Does not guarantee that your design is going to work, just that the device
will configure
Refer to the Spartan-6 FPGA Data Sheet or the Virtex-6 FPGA Data Sheet
FPGA and ASIC Technology
Comparison - 7
© 2009
2007 Xilinx, Inc. All Rights Reserved
Design-Dependent Power
 It is up to the user to plan on how much current their system can use
– This is dependent on the design, FPGA, and other devices used in your
system
 It is also up to you to anticipate how much your worst case power
consumption might be
– Xilinx provides descriptions of the current draw your FPGA might
have at power-up, during minimal operation, but not for worst-case
conditions
• Too much is design dependent (resources used, clock frequency, etc.)
 To get the best power estimate we offer a couple of power estimation
tools
– Please refer to the Power Estimation REL for more information
FPGA and ASIC Technology
Comparison - 8
© 2009
2007 Xilinx, Inc. All Rights Reserved
Estimating Power Consumption
 Power calculations can be performed at three distinct phases of the design
cycle
– Concept phase: A rough estimate of power can be calculated based on
estimates of logic capacity and activity rates
• Use the Xilinx Power Estimator spreadsheet
– Design phase: Power can be calculated more accurately based on detailed
information about how the design is implemented in the FPGA
• Use the XPower Analyzer
– System Integration phase: Power is calculated in a lab environment
• Use actual instrumentation
 Accurate power calculation at an early stage in the design cycle will result in
fewer problems later
FPGA and ASIC Technology
Comparison - 9
© 2009
2007 Xilinx, Inc. All Rights Reserved
Summary
 Static power is dependent on the transistor leakage current
 Dynamic power is dependent on the switching of the logic in the CLB array and IOB
resources
 Smaller device geometry increases the static power consumption of all devices
– Newer devices have a higher static power consumption
 An increase in junction temperature dramatically increases the leakage current and
your static power
 The minimum current required to operate and configure the FPGA is provided in
your FPGAs data sheet
– But the best way to estimate your power consumption is with either the Xilinx Power
Estimator spreadsheet or the XPower Analyzer utility
FPGA and ASIC Technology
Comparison - 10
© 2009
2007 Xilinx, Inc. All Rights Reserved
Where Can I Learn More?
 Xilinx online documents
– www.support.xilinx.com
• Spartan-6 FPGA Power Management User Guide, UG394
– Introduces the Suspend and Hibernate modes
– Describes the necessary voltage supplies
– Introduces the low-power (-1L) devices
– Describes the Power-On and Power-Down behavior
– Power Estimation options are discussed
FPGA and ASIC Technology
Comparison - 11
© 2009
2007 Xilinx, Inc. All Rights Reserved
Where Can I Learn More?
 Xilinx Training courses www.xilinx.com/training
– Designing with Spartan-6 and Virtex-6 Device Families course
•
•
•
•
How to get the most out of both device families
How to build the best HDL code for your FPGA design
How to optimize your design for Spartan-6 and/or Virtex-6
How to take advantage of the newest device features
 Free Video Based Training
–
–
–
–
How Do I Plan to Power My FPGA?
Power Estimation
What are the Spartan-6 Power Management Features?
What are the Virtex-6 Power Management Features?
FPGA and ASIC Technology
Comparison - 12
© 2009
2007 Xilinx, Inc. All Rights Reserved
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FPGA and ASIC Technology
Comparison - 13
© 2009
2007 Xilinx, Inc. All Rights Reserved