Transcript FPGAs The Superior Solution to Custom Logic November, 1998

Challenges and opportunities
for FPGA platforms
Ivo Bolsens
Xilinx Research Labs
Thanks to
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Bill Carter
David Eden
Erich Goetting
Alireza Kaviani
Bernie New
Cameron Patterson
Steve Trimberger
Tim Tuan
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Overview
• FPGA’s ride the tide
• Opportunities
• Challenges
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ASICs buck the tide, FPGAs
ride the tide
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Process Technology
Performance
Architecture
Cost
Flexibility
Market trends
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Moore’s Law
A tale of two numbers : What process people
don’t tell you
CD
CD
Tox, Gate
Leakage
320nm
Gate
240nm
Source
160nm
Substrate
80nm
1.3
2.7
4.5
6.5
(nm)
Tox
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Drain
Channel
Leakage
Trend: Line Widths Smaller
Than the Wavelength of Light
Process Geometry (micron)
0.700
0.600
0.500
0.400
0.300
0.200
0.100
1988
1990
1992
1994
Optical Processing Wavelength
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1996
1998
2000
Process Geometry
2002
Painting a one cm line with a
three cm brush…
Courtesy : IBM
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Gate Oxide
Polysilicon Gate
Gate Oxide
Silicon crystal
• About 10 molecular layers of SiO2 for this 150nm example
• 90nm technology is about half the thickness
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Process Technology Feature Size (nm)
FPGA’s are ahead of the curve
350
Virtex-II FPGA to Market
1-Year Earlier
250
180
150
130
100
Cu/Low-K
Xilinx is developing 90nm in 2002
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97
SIA Roadmap
98
99
00
01
Year
Xilinx
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02
03
04
05
Where are we today
556
10Mb
125K
442
24
4
105K
340
3Mb
Logic Cells
168
Block RAM Multipliers
XC2V8000
= 350M tranistors
840Mb/s
LVDS
XC2VP125
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3.125Gb/s PowerPC
MGTs
CPUs
FPGAs are leading
Intel’s Roadmap
Source : Intel
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Gate count requirement for
ASICs
7
20
<3M
3-5M
>5M
Source: IMS
73
FPGAs can address very large part of the ASIC market today
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Performance requirement
for ASICs
10.8
53.9
38.5
<100Mhz
100-200Mhz
>200Mhz
Source: IMS 2000
FPGAs can address very large part of the ASIC market today
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A Decade of Progress
1000x
1000
Virtex-II
(excl. Block RAM)
100x
100
Capacity
Speed
Price
Virtex &
Virtex-E
(excl. Block RAM)
XC4000
10
10x
Spartan
1x1
1/91
1/92
1/93
1/94
1/95
1/96
Year
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1/97
1/98
1/99
1/00
1/01
The Cost/Volume Crossover
1000
Relative Cost
100
ASIC Cost
10
FPGA Cost
1
0.1
10
100
1,000
10,000
Unit Volume
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100,000
1,000K
Are Transistors Free?
1 pin
10,000X
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10,000 transistors
Performance Scaling
45
40
Delay (ps)
35
Gate Delay
30
Wire Delay (Al)
25
20
Total Delay (Al)
15
10
Wire Delay
(Cu+Low k)
5
0
0
200
400
600
800
1000
Total Delay
(Cu+Low k)
Line Width (nm)
Source: ITRS
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Localisation of storage and
computing
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l/2
3 3
Heat/area V /l
2
Tconnect (nsec) .l /l
2
Courtesy :IMEC
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Market Requirements
PC
Mainframe
Smart Things
>100 # / human
1
0.01
Compute
Power
+DSP
+Communications
+ Ambient
Intelligence
60
70
80
90
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10
Electronics Industry Dynamics
Market Size ($)
Residential Gateway
(Broadband access)
Satellite/Cable
+ Digital
NTSC
VCR
Custom
Features
(Pay-Per-View)
Cable Decoders
NTSC
NTSC
Smart cards
(DES)
Digital
VCR
NTSC
DES
ATAPI
DES
ATAPI
DBS
Dramatic
DOCSIS
increase
NTSC HomePNA
in new
DES
HomeRF
standards
ATAPI HomePLUG
Bluetooth
DBS
DOCSIS Hiperlan2
DSL...
• New Products
Time
– Take less time to reach high volumes
– Shorter Product Life Cycles
– Many standards / More Interoperability
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Complex ASIC Design
The Shrinking Window of Innovation
Interconnect Power Analysis 3%
Transistor Analysis 3%
Simulation 5%
Design
authoring 20%
Extraction 5%
Place and Route
17%
Synthesis
16%
Floorplanning 5%
Static Timing
Analysis
5%
Gate Simulation 7%
Simulation
14%
• Average iterations between design and layout = 20
(Source Electronic Systems Jan 99)
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Simpler/Faster Design Flows
ASIC
Flow
Design and
Verification
Spec
Silicon
Prototype
System
Integration
Design
Freeze
FPGA
Flow Spec
Design and
Verification
System
Integration
Design
Freeze
• 2:1 proven Time-to-Market Advantage
• No silicon design or verification steps
• More design flexibility through later design
freeze
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Silicon
Production
Today’s Product Lifecycle
Profit for first
Profit to Market
Reduced profit
for latecomers
Time
• 37% of new digital products were late to market
• Entering the market first can result in up to a 40% greater
total profit contribution over the product’s life vs. the #2
entrant
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Today’s Product Lifecycle
IRL extends
product life in market
Profit
Time
• 37% of new digital products were late to market
• Entering the market first can result in up to a 40% greater
total profit contribution over the product’s life vs. the #2
entrant
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Virtex-II Pro PowerPC Technology
Fetch &
Decode
I-Cache
PPC
16KB
Timers
and
Debug
Logic
MMU
PPCD-Cache
16KB
Execution Unit
32x32b GPR
ALU, MAC
IBM PowerPC™ 405 RISC CPU
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32-bit RISC CPU, Harvard Architecture
130nm CMOS with 1.5V Operation
456 Dhrystone MIPS at 300MHz
32 x 32-bit General Purpose Registers
Hardware Multiply / Divide
5-Stage Execution Pipeline
16KB D-Cache, 16KB I-Cache
Memory Management Unit (MMU)
High-Bandwidth Interface to Logic
Built-In Hardware Timers
Built-In JTAG Debug and Trace support
3.8 sq mm = 1% of 2VP100
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High Performance
1824
456
400
200
100
2 CPUs
800
Virtex-II Pro
PowerPC 405
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4 CPUs
912
1 CPU
Dhrystone MIPS
1600
220
Altera
Excalibur
Arm 9
“Low PowerPC”: 0.59mW/MIPS
400
Full-Custom IBM CPU Design
1.5V 130nm CMOS Technology
Low-K Dielectric
IP-Immersion
Power (mW)
300
100mW =
1 LED Indicator
200
100
…or 169 MIPS!
0
50
100 150
200 250 300
Performance (Dhrystone MIPS)
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350
400
IP-Immersion
Embed multiple IP blocks of arbitrary shape with
high-bandwidth connectivity to FPGA core logic, memory & I/O
Technologies Enabling IP-Immersion
Metal 9
Metal 8
Metal 7
Metal 6
Metal 5
Metal 4
PPC
Metal 3
PPC
Metal 2
Metal 1
Advanced hard-IP block
(e.g. PowerPC CPU)
Poly
Silicon Substrate
Active Interconnect™
Segmented Routing
Metal ‘Headroom’
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System Architecture Options
External
Devices
• “Logic-Centric Architecture”
External
Interfaces
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PPC
External
Devices
PPC
PowerPC Executes Entirely out of Cache
No FPGA Logic, Memory, or I/O Used
10-20 Pages of C-Code or More
Use as Complex Algorithmic Engine
• Web Server
• Encryption/Decryption
• Packet Processor
“CPU-Centric Architecture”
– PowerPC forms Heart of Embedded System
– On & Off-Chip Peripherals
– External Interfaces
• e.g. PCI, 3GIO, Gb Ethernet, ZBT SRAM
– CoreConnect™ On-Chip Bus
• Ties System Together
– Peripherals implemented in FPGA Logic
– Typically Runs Embedded OS
External
Interfaces
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HW acceleration
Virtex-II Pro
Code Stack (C++)
Concatenated FEC Engine
Control Tasks
PowerPC
Viterbi
Processor
RAM
Viterbi
Interleaver
ReedSolomon
Interleaver
Reed-Solomon
PowerPC with Application-Specific
Hardware Acceleration
Control Tasks
XTREME
The Virtex-II Pro Advantage
Processing™
Control Tasks
Traditional
Viterbi
Interleave Reed-Solomon
Processing time
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HW/SW Interfacing
6.4Gb/sec
6.4Gb/sec
Timers
Fetch & and
Decode Debug
Logic
I-Cache
16KB
MMU
D-Cache
16KB
Execution Unit
32x32b GPR
ALU, MAC
6.4Gb/sec
BlockRAMs
6.4Gb/sec
Acceleration
Logic
• Provides Specialized Connectivity
Between PowerPC & FPGA Logic
• Dual-Port BlockRAM Memory
– CPU & Logic Each Own 1
Port
• High-Bandwidth
– 6.4Gb/sec
• Low-Latency
• Non-Caching
– Designed for
Communications Data
Processing
• Enables PowerPC & FPGA Logic to
Work together on Complex
Problems
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• Micro-controller style interface
to fabric for control plane
applications
• Benefits:
– Up to 10x faster than memory
mapped interface
– Saves PLB bandwidth for code
execution
– Minimizes pipeline stalls
PLB
405
Core
Processor Block
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APU
Controller
Hardware
Coprocessor
APU Controller
Creating Complete
Communications Solutions
TCP
IP
MAC
PHY
Upper Layers
on PowerPC
TCP/IP Stack
on PowerPC
Link Layer in
FPGA Logic
(GbE MAC)
MAC
ftp
telnet
rlogin
mail
etc
RocketIO is PHY
(1000Base-SX/LX)
Gb Ethernet
(1000BaseLX/SX/CX)
TCP/IP
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Infiniband Example
CPU Makes Communications Practical, Easier, & Cheaper
InfiniBand TCA
built with
CPU + fabric
CPU Based Solution
8 Times Less Area
…or built
with fabric only
Sources: Intel, Xilinx
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Configurable Platform
Specify System Architecture
Create System Architecture
Define Addresses
Configure Peripherals
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™
The MicroBlaze
High Performance Soft CPU
UART
PPC 405
32-Bit RISC
130nm Process
300+ MHz Core
420 D MIPS
PPC 405
Interrupt
Controller
TM
tm
CoreConnect
Technology
32-Bit RISC
130nm Process
300+ MHz Core
420 D MIPS
Arbiter
Local
OPB
Bus
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Incremental Design
lessens the impact of design changes
– “Next Generation” technology
– Easy set-up through floorplanning
along HDL hierarchy boundaries
– Changes only affect the module
that was changed
– The remainder of the design stays
locked and intact
– Timing repeatability
• preserves routing
– Faster turnaround for localized design
changes
Xilinx Confidential
Partial Reconfigurability
FPGA Flexibility for the Field
011011
• Re-program part of an FPGA
while it’s still running
• Virtex-II and Virtex-E
Fixed
Logic
PR
Logic
PR
Logic
Fixed
Logic
Fixed
Logic
User Definable
Boundaries
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System Exploration
Bus
Line
System
System
System
Payload
Interfaces
Processing
Payload
Payload
Data
Line
Assembly
Qualify
Format
Coding
Payload
Payload
Data
Line
Buffer
Quality
Alignment
Decoding
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Tx
Rx
Traditional Architecture
Payload
Assembly
Payload
Qualify
Data
Format
Line
Coding
Payload
Buffer
Payload
Quality
Data
Alignment
Line
Decoding
RAM
Tx
Rx
mP Bus Motorola PowerQUICC
System
U-Bus CPM
Memory
Interface
AAL5
Processor
G704
Framer
G703
LIU
FLASH
EEPROM
Processor
PCI Bus
System
Payload
Processing
Other Peripherals
MPC860
PCI Bridge
Device
CPM = Communications Processor Module
Generic Design
System
Interfaces
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Traditional Architecture
Payload
Assembly
Payload
Qualify
Data
Format
Line
Coding
Payload
Buffer
Payload
Quality
Data
Alignment
Line
Decoding
mP Bus
System
Tx
Rx
Motorola PowerQUICC
U-Bus
RAM
Memory
Interface
CPM
AAL5
Processor
G704
Framer
G703
LIU
Data
Direction
FLASH
EEPROM
Processor
PCI Bus
System
Payload
Processing
Other Peripherals
MPC860
PCI Bridge
Device
CPM = Communications Processor Module
Generic Design
System
Interfaces
Xilinx Confidential
Optimized Architecture
Payload
Assembly
Payload
Qualify
Data
Format
Line
Coding
Payload
Buffer
Payload
Quality
Data
Alignment
Line
Decoding
Tx
Rx
mP Bus
System
RAM
FLASH
Dual Port
Block
RAM
MicroB
Processor
G704
Framer
G703
LIU
EEPROM
Memory
Interface
PCI Bus
System
PowerPC
Processor
Other Peripherals
PCI Bridge
Device
Fast I/F
FIFO
FPGA Boundary
Generic Design
System
Interfaces
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Payload
Processing
Optimized Architecture
Payload
Assembly
Payload
Qualify
Data
Format
Line
Coding
Payload
Buffer
Payload
Quality
Data
Alignment
Line
Decoding
Tx
Rx
mP Bus
System
RAM
FLASH
Dual Port
Block
RAM
MicroB
Processor
G704
Framer
G703
LIU
EEPROM
Memory
Interface
PCI Bus
System
PowerPC
Processor
Other Peripherals
PCI Bridge
Device
Fast I/F
FIFO
FPGA Boundary
Generic Design
System
Interfaces
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Payload
Processing
Interconnect and power
Source : Bill Daly
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Interconnect and
performance
Source : Bill Daly
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Power Analysis
• Typical design
– 5.9uW/CLB/MHz [FPGA00]
– Fabric power is ~69% of total power
– 2V6000 = 5.9uW/CLB/MHz  8448CLBs
 100MHz  69% = 7.5W
Mult
11%
BRAM
13%
IOB
7%
Fabric
69%
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Dynamic Power
• Normalized to 2001
– Best fit is a quadratic trend line
– Predicts 5X by 2007
Dynamic Power
1996: 4000EX
1997: 4000XL
1998: 4000XV
1999: Virtex
2000: Virtex-E
2001: Virtex-II
6
5
4
3
2
1
0
1994
1996
1998
2000
2002
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2004
2006
2008
Static Power
• Normalized to 2001
– Best fit is a power trend
– Predicts 100X by 2007
• Future data points projected
Staticusing
Power linear trend for 1/VTH
1000
100
10
1
0.1
0
2
4
6
8
10
12
0.01
\
0.001
0.0001
0.00001
0.000001
1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
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Static versus Dynamic
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The Age of Accumulation
Mixed
Signal
uProc.
System
Clock
Management
High
Performance
I/O
Memory
Special
Arithmetic
Functions
Gates
Routing
Virtex-II Pro
Virtex
Virtex
XC4000
XC4000
XC2000
Xilinx Confidential
FPGA
Incremental Design
lessens the impact of design changes
– “Next Generation” technology
– Easy set-up through floorplanning
along HDL hierarchy boundaries
– Changes only affect the module
that was changed
– The remainder of the design stays
locked and intact
– Timing repeatability
• preserves routing
– Faster turnaround for localized design
changes
“New in ISE5.1i”
Xilinx Confidential
Partial Reconfigurability
FPGA Flexibility for the Field
011011
• Re-program part of an FPGA
while it’s still running
• Virtex-II and Virtex-E
Fixed
Logic
PR
Logic
PR
Logic
Fixed
Logic
Fixed
Logic
User Definable
Boundaries
Xilinx Confidential
System Level Design Flow
Functional
Modeling
IP
Models
Architectural
Exploration
Behavioral C/C++
System Design
and Partitioning
Formal/ Plug&Play
Implementation
Architecture
ANSI C/C++
Embedded
Software
HW-SW Codesign
Enabling
Technologies
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Cycle-Accurate C/C++
HW Synthesis
HDL
Reconfigurability : 4th
dimension
• Applications open, close,
and change priority
over time
• Use model : ObjectOriented
Multiprocessing
Application 4
Application 3
Memory
Application 2
Memory
Prog H/W
Object
S/W
Memory
Prog H/W
Object
Object
S/W
Memory
Prog H/W
Object
ObjectFixed H/W
S/W
Prog H/W
Object
Object
Fixed
H/W
Object
S/W
Object
Object
Fixed H/W
Object
Fixed H/W
Object
Application 1
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The mother of all complex flows
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No established formal models / semantics
Design capture and simulation issues
Hardware/software co-design
Modular design with uniform interfaces
Dynamic management of diverse hardware resources
creates new place & route issues
– Bitstream production, storage, loading and linking
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Combining the Best of
FPGA and ASIC: XBlue
PowerPC
Core
Embedded
FPGA Core
Special
Functions
Block
RAM
Block
RAM
100% Fixed Logic
100% Programmable
Traditional ASIC Market
Traditional FPGA Market
• Inflexible, but highest
performance/integration
• Flexible, but expensive
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Conclusions
• FPGA’s ride the tide
• Today : Programmable System Platform
• Challenges
–
–
–
–
Design Technology
Interconnect
Low Power
Exploit 3rd and 4th dimension
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